[RESEND,v2,1/4] media: chips-media: wave5: Support SPS/PPS generation for each IDR
Commit Message
From: "Jackson.lee" <jackson.lee@chipsnmedia.com>
Provide a control to toggle (0 = off / 1 = on), whether the SPS and
PPS are generated for every IDR.
Signed-off-by: Jackson.lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
---
.../platform/chips-media/wave5/wave5-hw.c | 19 +++++++++++++++----
.../chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
.../platform/chips-media/wave5/wave5-vpuapi.h | 1 +
3 files changed, 23 insertions(+), 4 deletions(-)
Comments
Le lundi 11 mars 2024 à 19:56 +0900, jackson.lee a écrit :
> From: "Jackson.lee" <jackson.lee@chipsnmedia.com>
>
> Provide a control to toggle (0 = off / 1 = on), whether the SPS and
> PPS are generated for every IDR.
>
> Signed-off-by: Jackson.lee <jackson.lee@chipsnmedia.com>
> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
> ---
> .../platform/chips-media/wave5/wave5-hw.c | 19 +++++++++++++++----
> .../chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
> .../platform/chips-media/wave5/wave5-vpuapi.h | 1 +
> 3 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> index f1e022fb148e..4a262822bf17 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> @@ -23,6 +23,15 @@
> #define FEATURE_AVC_ENCODER BIT(1)
> #define FEATURE_HEVC_ENCODER BIT(0)
>
> +#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff
> +#define ENC_AVC_INTRA_PERIOD 6
> +#define ENC_AVC_IDR_PERIOD 17
> +#define ENC_AVC_FORCED_IDR_HEADER 28
> +
> +#define ENC_HEVC_INTRA_QP 3
> +#define ENC_HEVC_FORCED_IDR_HEADER 9
> +#define ENC_HEVC_INTRA_PERIOD 16
> +
Perhaps add the suffix _SHIFT to these macro ? I think it can easily be confused
with a default value otherwise.
nit: can happen later, since this is how things got merged in this driver, but
typically, registers offsets, shift and masks are usually consolidated in a
single reg header. It would be nice to consider cleaning this up in future
patches.
> /* Decoder support fields */
> #define FEATURE_AVC_DECODER BIT(3)
> #define FEATURE_HEVC_DECODER BIT(2)
> @@ -1601,12 +1610,14 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
>
> if (inst->std == W_AVC_ENC)
> vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
> - ((p_param->intra_period & 0x7ff) << 6) |
> - ((p_param->avc_idr_period & 0x7ff) << 17));
> + ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_INTRA_PERIOD) |
> + ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_IDR_PERIOD) |
> + (p_param->forced_idr_header_enable << ENC_AVC_FORCED_IDR_HEADER));
> else if (inst->std == W_HEVC_ENC)
> vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
> - p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
> - (p_param->intra_period << 16));
> + p_param->decoding_refresh_type | (p_param->intra_qp << ENC_HEVC_INTRA_QP) |
> + (p_param->forced_idr_header_enable << ENC_HEVC_FORCED_IDR_HEADER) |
> + (p_param->intra_period << ENC_HEVC_INTRA_PERIOD));
>
> reg_val = (p_param->rdo_skip << 2) |
> (p_param->lambda_scaling_enable << 3) |
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> index f29cfa3af94a..f04baa93a9b7 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> @@ -1061,6 +1061,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
> case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
> inst->enc_param.entropy_coding_mode = ctrl->val;
> break;
> + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
> + inst->enc_param.forced_idr_header_enable = ctrl->val;
> + break;
> case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
> break;
> default:
> @@ -1219,6 +1222,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param,
> else
> open_param->wave_param.intra_refresh_arg = num_ctu_row;
> }
> + open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable;
in the long term, there is one too many abstraction in this driver, we should
remove that.
> }
>
> static int initialize_sequence(struct vpu_instance *inst)
> @@ -1702,6 +1706,9 @@ static int wave5_vpu_open_enc(struct file *filp)
> 0, 1, 1, 0);
> v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
> + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
> + 0, 1, 1, 0);
>
> if (v4l2_ctrl_hdl->error) {
> ret = -ENODEV;
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> index 352f6e904e50..3ad6118550ac 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> @@ -566,6 +566,7 @@ struct enc_wave_param {
> u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
> u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
> u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
> + u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
> };
>
> struct enc_open_param {
With the suggested _SHIFT suffix (or equivalent) added.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Hi Nicolas
Thanks for your review.
I will add the suffix into next patch.
> -----Original Message-----
> From: Nicolas Dufresne <nicolas@ndufresne.ca>
> Sent: Friday, April 19, 2024 5:43 AM
> To: jackson.lee <jackson.lee@chipsnmedia.com>; mchehab@kernel.org;
> sebastian.fricke@collabora.com
> Cc: linux-media@vger.kernel.org; linux-kernel@vger.kernel.org;
> hverkuil@xs4all.nl; Nas Chung <nas.chung@chipsnmedia.com>; lafley.kim
> <lafley.kim@chipsnmedia.com>; b-brnich@ti.com
> Subject: Re: [RESEND PATCH v2 1/4] media: chips-media: wave5: Support SPS/PPS
> generation for each IDR
>
> Le lundi 11 mars 2024 à 19:56 +0900, jackson.lee a écrit :
> > From: "Jackson.lee" <jackson.lee@chipsnmedia.com>
> >
> > Provide a control to toggle (0 = off / 1 = on), whether the SPS and
> > PPS are generated for every IDR.
> >
> > Signed-off-by: Jackson.lee <jackson.lee@chipsnmedia.com>
> > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
> > ---
> > .../platform/chips-media/wave5/wave5-hw.c | 19 +++++++++++++++----
> > .../chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
> > .../platform/chips-media/wave5/wave5-vpuapi.h | 1 +
> > 3 files changed, 23 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> > b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> > index f1e022fb148e..4a262822bf17 100644
> > --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> > +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> > @@ -23,6 +23,15 @@
> > #define FEATURE_AVC_ENCODER BIT(1)
> > #define FEATURE_HEVC_ENCODER BIT(0)
> >
> > +#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff
> > +#define ENC_AVC_INTRA_PERIOD 6
> > +#define ENC_AVC_IDR_PERIOD 17
> > +#define ENC_AVC_FORCED_IDR_HEADER 28
> > +
> > +#define ENC_HEVC_INTRA_QP 3
> > +#define ENC_HEVC_FORCED_IDR_HEADER 9
> > +#define ENC_HEVC_INTRA_PERIOD 16
> > +
>
> Perhaps add the suffix _SHIFT to these macro ? I think it can easily be
> confused with a default value otherwise.
>
> nit: can happen later, since this is how things got merged in this driver,
> but typically, registers offsets, shift and masks are usually consolidated in
> a single reg header. It would be nice to consider cleaning this up in future
> patches.
>
> > /* Decoder support fields */
> > #define FEATURE_AVC_DECODER BIT(3)
> > #define FEATURE_HEVC_DECODER BIT(2)
> > @@ -1601,12 +1610,14 @@ int wave5_vpu_enc_init_seq(struct vpu_instance
> > *inst)
> >
> > if (inst->std == W_AVC_ENC)
> > vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param-
> >intra_qp |
> > - ((p_param->intra_period & 0x7ff) << 6) |
> > - ((p_param->avc_idr_period & 0x7ff) << 17));
> > + ((p_param->intra_period &
> ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_INTRA_PERIOD) |
> > + ((p_param->avc_idr_period &
> ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_IDR_PERIOD) |
> > + (p_param->forced_idr_header_enable <<
> > +ENC_AVC_FORCED_IDR_HEADER));
> > else if (inst->std == W_HEVC_ENC)
> > vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
> > - p_param->decoding_refresh_type | (p_param->intra_qp
> << 3) |
> > - (p_param->intra_period << 16));
> > + p_param->decoding_refresh_type | (p_param->intra_qp
> << ENC_HEVC_INTRA_QP) |
> > + (p_param->forced_idr_header_enable <<
> ENC_HEVC_FORCED_IDR_HEADER) |
> > + (p_param->intra_period << ENC_HEVC_INTRA_PERIOD));
> >
> > reg_val = (p_param->rdo_skip << 2) |
> > (p_param->lambda_scaling_enable << 3) | diff --git
> > a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> > b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> > index f29cfa3af94a..f04baa93a9b7 100644
> > --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> > @@ -1061,6 +1061,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl
> *ctrl)
> > case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
> > inst->enc_param.entropy_coding_mode = ctrl->val;
> > break;
> > + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
> > + inst->enc_param.forced_idr_header_enable = ctrl->val;
> > + break;
> > case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
> > break;
> > default:
> > @@ -1219,6 +1222,7 @@ static void wave5_set_enc_openparam(struct
> enc_open_param *open_param,
> > else
> > open_param->wave_param.intra_refresh_arg = num_ctu_row;
> > }
> > + open_param->wave_param.forced_idr_header_enable =
> > +input.forced_idr_header_enable;
>
> in the long term, there is one too many abstraction in this driver, we should
> remove that.
>
> > }
> >
> > static int initialize_sequence(struct vpu_instance *inst) @@ -1702,6
> > +1706,9 @@ static int wave5_vpu_open_enc(struct file *filp)
> > 0, 1, 1, 0);
> > v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> > V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
> > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> > + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
> > + 0, 1, 1, 0);
> >
> > if (v4l2_ctrl_hdl->error) {
> > ret = -ENODEV;
> > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> > b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> > index 352f6e904e50..3ad6118550ac 100644
> > --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> > @@ -566,6 +566,7 @@ struct enc_wave_param {
> > u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom
> GOP */
> > u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8
> transform */
> > u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
> > + u32 forced_idr_header_enable: 1; /* enable header encoding before
> > +IDR frame */
> > };
> >
> > struct enc_open_param {
>
> With the suggested _SHIFT suffix (or equivalent) added.
>
> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
@@ -23,6 +23,15 @@
#define FEATURE_AVC_ENCODER BIT(1)
#define FEATURE_HEVC_ENCODER BIT(0)
+#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff
+#define ENC_AVC_INTRA_PERIOD 6
+#define ENC_AVC_IDR_PERIOD 17
+#define ENC_AVC_FORCED_IDR_HEADER 28
+
+#define ENC_HEVC_INTRA_QP 3
+#define ENC_HEVC_FORCED_IDR_HEADER 9
+#define ENC_HEVC_INTRA_PERIOD 16
+
/* Decoder support fields */
#define FEATURE_AVC_DECODER BIT(3)
#define FEATURE_HEVC_DECODER BIT(2)
@@ -1601,12 +1610,14 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
if (inst->std == W_AVC_ENC)
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
- ((p_param->intra_period & 0x7ff) << 6) |
- ((p_param->avc_idr_period & 0x7ff) << 17));
+ ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_INTRA_PERIOD) |
+ ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_IDR_PERIOD) |
+ (p_param->forced_idr_header_enable << ENC_AVC_FORCED_IDR_HEADER));
else if (inst->std == W_HEVC_ENC)
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
- p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
- (p_param->intra_period << 16));
+ p_param->decoding_refresh_type | (p_param->intra_qp << ENC_HEVC_INTRA_QP) |
+ (p_param->forced_idr_header_enable << ENC_HEVC_FORCED_IDR_HEADER) |
+ (p_param->intra_period << ENC_HEVC_INTRA_PERIOD));
reg_val = (p_param->rdo_skip << 2) |
(p_param->lambda_scaling_enable << 3) |
@@ -1061,6 +1061,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
inst->enc_param.entropy_coding_mode = ctrl->val;
break;
+ case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
+ inst->enc_param.forced_idr_header_enable = ctrl->val;
+ break;
case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
break;
default:
@@ -1219,6 +1222,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param,
else
open_param->wave_param.intra_refresh_arg = num_ctu_row;
}
+ open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable;
}
static int initialize_sequence(struct vpu_instance *inst)
@@ -1702,6 +1706,9 @@ static int wave5_vpu_open_enc(struct file *filp)
0, 1, 1, 0);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
+ v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
+ V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
+ 0, 1, 1, 0);
if (v4l2_ctrl_hdl->error) {
ret = -ENODEV;
@@ -566,6 +566,7 @@ struct enc_wave_param {
u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
+ u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
};
struct enc_open_param {