diff mbox series

[RESEND,v0,2/5] wave5: Support to prepend sps/pps to IDR frame.

Message ID 20240131013046.15687-3-jackson.lee@chipsnmedia.com (mailing list archive)
State Superseded
Delegated to: Sebastian Fricke
Headers
Series wave5 codec driver |

Commit Message

jackson.lee Jan. 31, 2024, 1:30 a.m. UTC 
  Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 disables generating SPS and PPS at every IDR.
Setting it to one enables generating SPS and PPS at every IDR.

Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
---
 drivers/media/platform/chips-media/wave5/wave5-hw.c      | 6 ++++--
 drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
 drivers/media/platform/chips-media/wave5/wave5-vpuapi.h  | 1 +
 3 files changed, 12 insertions(+), 2 deletions(-)

Comments

Nicolas Dufresne Feb. 7, 2024, 6 p.m. UTC | #1 
Hi Jackson,

Le mercredi 31 janvier 2024 à 10:30 +0900, jackson.lee a écrit :
> Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 disables generating SPS and PPS at every IDR.
> Setting it to one enables generating SPS and PPS at every IDR.
> 
> Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
> ---
>  drivers/media/platform/chips-media/wave5/wave5-hw.c      | 6 ++++--
>  drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
>  drivers/media/platform/chips-media/wave5/wave5-vpuapi.h  | 1 +
>  3 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> index f1e022fb148e..8ad7f3a28ae1 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> @@ -1602,11 +1602,13 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
>  	if (inst->std == W_AVC_ENC)
>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
>  				((p_param->intra_period & 0x7ff) << 6) |
> -				((p_param->avc_idr_period & 0x7ff) << 17));
> +				((p_param->avc_idr_period & 0x7ff) << 17) |
> +				(p_param->forced_idr_header_enable << 28));

I can spot evident hard-coding of mask and bit shifts in here. In order to
continuously improve this driver code, I would like to see this (and the
following) magic number being defined with well named macros as a preparation
patch to this feature change.

regards,
Nicolas

>  	else if (inst->std == W_HEVC_ENC)
>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
>  			      p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
> -				(p_param->intra_period << 16));
> +			      (p_param->forced_idr_header_enable << 9) |
> +			      (p_param->intra_period << 16));
>  
>  	reg_val = (p_param->rdo_skip << 2) |
>  		(p_param->lambda_scaling_enable << 3) |
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> index 0cb5bfb67258..761775216cd4 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> @@ -1125,6 +1125,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
>  	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
>  		inst->enc_param.entropy_coding_mode = ctrl->val;
>  		break;
> +	case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
> +		inst->enc_param.forced_idr_header_enable = ctrl->val;
> +		break;
>  	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
>  		break;
>  	default:
> @@ -1292,6 +1295,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param,
>  		else
>  			open_param->wave_param.intra_refresh_arg = num_ctu_row;
>  	}
> +	open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable;
>  }
>  
>  static int initialize_sequence(struct vpu_instance *inst)
> @@ -1775,6 +1779,9 @@ static int wave5_vpu_open_enc(struct file *filp)
>  			  0, 1, 1, 0);
>  	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
>  			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
> +	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> +			  V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
> +			  0, 1, 1, 0);
>  
>  	if (v4l2_ctrl_hdl->error) {
>  		ret = -ENODEV;
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> index 352f6e904e50..3ad6118550ac 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> @@ -566,6 +566,7 @@ struct enc_wave_param {
>  	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
>  	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
>  	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
> +	u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
>  };
>  
>  struct enc_open_param {
sebastian.fricke@collabora.com Feb. 8, 2024, 10:01 a.m. UTC | #2 
Hey Jackson,

as with the previous review, the title needs to be adjusted 'wave5:' is
not enough.
Also 'Support to prepend sps/pps to IDR' sounds a bit weird and doesn't
quite match what you describe below.
How about:
'Support SPS/PPS generation for each IDR'

On 07.02.2024 13:00, Nicolas Dufresne wrote:
>Hi Jackson,
>
>Le mercredi 31 janvier 2024 à 10:30 +0900, jackson.lee a écrit :
>> Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 disables generating SPS and PPS at every IDR.
>> Setting it to one enables generating SPS and PPS at every IDR.

My suggestion:

Provide a control to toggle (0 = off / 1 = on), whether the SPS and PPS
are generated for every IDR.

Greetings,
Sebastian

>>
>> Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
>> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
>> ---
>>  drivers/media/platform/chips-media/wave5/wave5-hw.c      | 6 ++++--
>>  drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
>>  drivers/media/platform/chips-media/wave5/wave5-vpuapi.h  | 1 +
>>  3 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
>> index f1e022fb148e..8ad7f3a28ae1 100644
>> --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
>> +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
>> @@ -1602,11 +1602,13 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
>>  	if (inst->std == W_AVC_ENC)
>>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
>>  				((p_param->intra_period & 0x7ff) << 6) |
>> -				((p_param->avc_idr_period & 0x7ff) << 17));
>> +				((p_param->avc_idr_period & 0x7ff) << 17) |
>> +				(p_param->forced_idr_header_enable << 28));
>
>I can spot evident hard-coding of mask and bit shifts in here. In order to
>continuously improve this driver code, I would like to see this (and the
>following) magic number being defined with well named macros as a preparation
>patch to this feature change.
>
>regards,
>Nicolas
>
>>  	else if (inst->std == W_HEVC_ENC)
>>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
>>  			      p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
>> -				(p_param->intra_period << 16));
>> +			      (p_param->forced_idr_header_enable << 9) |
>> +			      (p_param->intra_period << 16));
>>
>>  	reg_val = (p_param->rdo_skip << 2) |
>>  		(p_param->lambda_scaling_enable << 3) |
>> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
>> index 0cb5bfb67258..761775216cd4 100644
>> --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
>> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
>> @@ -1125,6 +1125,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
>>  	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
>>  		inst->enc_param.entropy_coding_mode = ctrl->val;
>>  		break;
>> +	case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
>> +		inst->enc_param.forced_idr_header_enable = ctrl->val;
>> +		break;
>>  	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
>>  		break;
>>  	default:
>> @@ -1292,6 +1295,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param,
>>  		else
>>  			open_param->wave_param.intra_refresh_arg = num_ctu_row;
>>  	}
>> +	open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable;
>>  }
>>
>>  static int initialize_sequence(struct vpu_instance *inst)
>> @@ -1775,6 +1779,9 @@ static int wave5_vpu_open_enc(struct file *filp)
>>  			  0, 1, 1, 0);
>>  	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
>>  			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
>> +	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
>> +			  V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
>> +			  0, 1, 1, 0);
>>
>>  	if (v4l2_ctrl_hdl->error) {
>>  		ret = -ENODEV;
>> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
>> index 352f6e904e50..3ad6118550ac 100644
>> --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
>> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
>> @@ -566,6 +566,7 @@ struct enc_wave_param {
>>  	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
>>  	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
>>  	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
>> +	u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
>>  };
>>
>>  struct enc_open_param {
>
>
jackson.lee Feb. 16, 2024, 7:12 a.m. UTC | #3 
Hello Sebastian

Thanks your review, we will review your advice.

> -----Original Message-----
> From: Sebastian Fricke <sebastian.fricke@collabora.com>
> Sent: Thursday, February 8, 2024 7:02 PM
> To: Nicolas Dufresne <nicolas@ndufresne.ca>
> Cc: jackson.lee <jackson.lee@chipsnmedia.com>; mchehab@kernel.org; linux-
> media@vger.kernel.org; linux-kernel@vger.kernel.org; Nas Chung
> <nas.chung@chipsnmedia.com>; lafley.kim <lafley.kim@chipsnmedia.com>; b-
> brnich@ti.com
> Subject: Re: [RESEND PATCH v0 2/5] wave5: Support to prepend sps/pps to
> IDR frame.
> 
> Hey Jackson,
> 
> as with the previous review, the title needs to be adjusted 'wave5:' is
> not enough.
> Also 'Support to prepend sps/pps to IDR' sounds a bit weird and doesn't
> quite match what you describe below.
> How about:
> 'Support SPS/PPS generation for each IDR'
> 
> On 07.02.2024 13:00, Nicolas Dufresne wrote:
> >Hi Jackson,
> >
> >Le mercredi 31 janvier 2024 à 10:30 +0900, jackson.lee a écrit :
> >> Indicates whether to generate SPS and PPS at every IDR. Setting it to 0
> disables generating SPS and PPS at every IDR.
> >> Setting it to one enables generating SPS and PPS at every IDR.
> 
> My suggestion:
> 
> Provide a control to toggle (0 = off / 1 = on), whether the SPS and PPS
> are generated for every IDR.
> 
> Greetings,
> Sebastian
> 
> >>
> >> Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
> >> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
> >> ---
> >>  drivers/media/platform/chips-media/wave5/wave5-hw.c      | 6 ++++--
> >>  drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 7 +++++++
> >> drivers/media/platform/chips-media/wave5/wave5-vpuapi.h  | 1 +
> >>  3 files changed, 12 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> >> b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> >> index f1e022fb148e..8ad7f3a28ae1 100644
> >> --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> >> +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> >> @@ -1602,11 +1602,13 @@ int wave5_vpu_enc_init_seq(struct vpu_instance
> *inst)
> >>  	if (inst->std == W_AVC_ENC)
> >>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
> p_param->intra_qp |
> >>  				((p_param->intra_period & 0x7ff) << 6) |
> >> -				((p_param->avc_idr_period & 0x7ff) << 17));
> >> +				((p_param->avc_idr_period & 0x7ff) << 17) |
> >> +				(p_param->forced_idr_header_enable << 28));
> >
> >I can spot evident hard-coding of mask and bit shifts in here. In order
> >to continuously improve this driver code, I would like to see this (and
> >the
> >following) magic number being defined with well named macros as a
> >preparation patch to this feature change.
> >
> >regards,
> >Nicolas
> >
> >>  	else if (inst->std == W_HEVC_ENC)
> >>  		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
> >>  			      p_param->decoding_refresh_type | (p_param-
> >intra_qp << 3) |
> >> -				(p_param->intra_period << 16));
> >> +			      (p_param->forced_idr_header_enable << 9) |
> >> +			      (p_param->intra_period << 16));
> >>
> >>  	reg_val = (p_param->rdo_skip << 2) |
> >>  		(p_param->lambda_scaling_enable << 3) | diff --git
> >> a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> >> b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> >> index 0cb5bfb67258..761775216cd4 100644
> >> --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> >> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> >> @@ -1125,6 +1125,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl
> *ctrl)
> >>  	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
> >>  		inst->enc_param.entropy_coding_mode = ctrl->val;
> >>  		break;
> >> +	case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
> >> +		inst->enc_param.forced_idr_header_enable = ctrl->val;
> >> +		break;
> >>  	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
> >>  		break;
> >>  	default:
> >> @@ -1292,6 +1295,7 @@ static void wave5_set_enc_openparam(struct
> enc_open_param *open_param,
> >>  		else
> >>  			open_param->wave_param.intra_refresh_arg = num_ctu_row;
> >>  	}
> >> +	open_param->wave_param.forced_idr_header_enable =
> >> +input.forced_idr_header_enable;
> >>  }
> >>
> >>  static int initialize_sequence(struct vpu_instance *inst) @@ -1775,6
> >> +1779,9 @@ static int wave5_vpu_open_enc(struct file *filp)
> >>  			  0, 1, 1, 0);
> >>  	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> >>  			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
> >> +	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> >> +			  V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
> >> +			  0, 1, 1, 0);
> >>
> >>  	if (v4l2_ctrl_hdl->error) {
> >>  		ret = -ENODEV;
> >> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> >> b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> >> index 352f6e904e50..3ad6118550ac 100644
> >> --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> >> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> >> @@ -566,6 +566,7 @@ struct enc_wave_param {
> >>  	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom
> GOP */
> >>  	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8
> transform */
> >>  	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
> >> +	u32 forced_idr_header_enable: 1; /* enable header encoding before
> >> +IDR frame */
> >>  };
> >>
> >>  struct enc_open_param {
> >
> >
diff mbox series

Patch

diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
index f1e022fb148e..8ad7f3a28ae1 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
@@ -1602,11 +1602,13 @@  int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
 	if (inst->std == W_AVC_ENC)
 		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
 				((p_param->intra_period & 0x7ff) << 6) |
-				((p_param->avc_idr_period & 0x7ff) << 17));
+				((p_param->avc_idr_period & 0x7ff) << 17) |
+				(p_param->forced_idr_header_enable << 28));
 	else if (inst->std == W_HEVC_ENC)
 		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
 			      p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
-				(p_param->intra_period << 16));
+			      (p_param->forced_idr_header_enable << 9) |
+			      (p_param->intra_period << 16));
 
 	reg_val = (p_param->rdo_skip << 2) |
 		(p_param->lambda_scaling_enable << 3) |
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
index 0cb5bfb67258..761775216cd4 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
@@ -1125,6 +1125,9 @@  static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
 	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
 		inst->enc_param.entropy_coding_mode = ctrl->val;
 		break;
+	case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
+		inst->enc_param.forced_idr_header_enable = ctrl->val;
+		break;
 	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
 		break;
 	default:
@@ -1292,6 +1295,7 @@  static void wave5_set_enc_openparam(struct enc_open_param *open_param,
 		else
 			open_param->wave_param.intra_refresh_arg = num_ctu_row;
 	}
+	open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable;
 }
 
 static int initialize_sequence(struct vpu_instance *inst)
@@ -1775,6 +1779,9 @@  static int wave5_vpu_open_enc(struct file *filp)
 			  0, 1, 1, 0);
 	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
 			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);
+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
+			  V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR,
+			  0, 1, 1, 0);
 
 	if (v4l2_ctrl_hdl->error) {
 		ret = -ENODEV;
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
index 352f6e904e50..3ad6118550ac 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
@@ -566,6 +566,7 @@  struct enc_wave_param {
 	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
 	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
 	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
+	u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
 };
 
 struct enc_open_param {