[09/16] media: ti-vpe: cal: cleanup CIO power enable/disable
Commit Message
Move the code to enable and disable ComplexIO power to its own function.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
drivers/media/platform/ti-vpe/cal.c | 68 ++++++++++++++---------------
1 file changed, 32 insertions(+), 36 deletions(-)
Comments
Hi Tomi,
Thank you for the patch.
On Fri, Mar 13, 2020 at 01:41:14PM +0200, Tomi Valkeinen wrote:
> Move the code to enable and disable ComplexIO power to its own function.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/media/platform/ti-vpe/cal.c | 68 ++++++++++++++---------------
> 1 file changed, 32 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index ebea5fa28691..771ad7c14c96 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -731,11 +731,40 @@ static void disable_irqs(struct cal_ctx *ctx)
> reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0);
> }
>
> +static void csi2_cio_pwr(struct cal_ctx *ctx, bool enable)
I think you can spell it out fully to csi2_cio_power.
> +{
> + u32 target_state;
> + int i;
i is never negative, it can be an unsued int.
> +
> + target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
> + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
> +
> + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> + target_state,
> + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
These two liens would hold on a single line.
> +
> + for (i = 0; i < 10; i++) {
> + u32 current_state;
> +
> + current_state = reg_read_field(ctx->dev,
> + CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> + CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
> +
> + if (current_state == target_state)
> + break;
> +
> + usleep_range(1000, 1100);
> + }
> +
> + if (i == 10)
> + ctx_err(ctx, "Failed to power %s complexio\n",
> + enable ? "up" : "down");
> +}
> +
> static void csi2_phy_config(struct cal_ctx *ctx);
>
> static void csi2_phy_init(struct cal_ctx *ctx)
> {
> - int i;
> u32 val;
>
> /* Steps
> @@ -790,23 +819,7 @@ static void csi2_phy_init(struct cal_ctx *ctx)
> reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)));
>
> /* E. Power up the PHY using the complex IO */
> - reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON,
> - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
> -
> - /* F. Wait for power up completion */
> - for (i = 0; i < 10; i++) {
> - if (reg_read_field(ctx->dev,
> - CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
> - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON)
> - break;
> - usleep_range(1000, 1100);
> - }
> - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered UP %s\n",
> - ctx->csi2_port,
> - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)),
> - (i >= 10) ? "(timeout)" : "");
> + csi2_cio_pwr(ctx, true);
> }
>
> static void csi2_wait_for_phy(struct cal_ctx *ctx)
> @@ -865,24 +878,7 @@ static void csi2_phy_deinit(struct cal_ctx *ctx)
> {
> int i;
>
> - /* Power down the PHY using the complex IO */
> - reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF,
> - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
> -
> - /* Wait for power down completion */
> - for (i = 0; i < 10; i++) {
> - if (reg_read_field(ctx->dev,
> - CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
> - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF)
> - break;
> - usleep_range(1000, 1100);
> - }
> - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered Down %s\n",
> - ctx->csi2_port,
> - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)),
> - (i >= 10) ? "(timeout)" : "");
> + csi2_cio_pwr(ctx, false);
>
> /* Assert Comple IO Reset */
> reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
@@ -731,11 +731,40 @@ static void disable_irqs(struct cal_ctx *ctx)
reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0);
}
+static void csi2_cio_pwr(struct cal_ctx *ctx, bool enable)
+{
+ u32 target_state;
+ int i;
+
+ target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
+ CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
+
+ reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
+ target_state,
+ CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
+
+ for (i = 0; i < 10; i++) {
+ u32 current_state;
+
+ current_state = reg_read_field(ctx->dev,
+ CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
+ CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
+
+ if (current_state == target_state)
+ break;
+
+ usleep_range(1000, 1100);
+ }
+
+ if (i == 10)
+ ctx_err(ctx, "Failed to power %s complexio\n",
+ enable ? "up" : "down");
+}
+
static void csi2_phy_config(struct cal_ctx *ctx);
static void csi2_phy_init(struct cal_ctx *ctx)
{
- int i;
u32 val;
/* Steps
@@ -790,23 +819,7 @@ static void csi2_phy_init(struct cal_ctx *ctx)
reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)));
/* E. Power up the PHY using the complex IO */
- reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON,
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
-
- /* F. Wait for power up completion */
- for (i = 0; i < 10; i++) {
- if (reg_read_field(ctx->dev,
- CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
- CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
- CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON)
- break;
- usleep_range(1000, 1100);
- }
- ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered UP %s\n",
- ctx->csi2_port,
- reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)),
- (i >= 10) ? "(timeout)" : "");
+ csi2_cio_pwr(ctx, true);
}
static void csi2_wait_for_phy(struct cal_ctx *ctx)
@@ -865,24 +878,7 @@ static void csi2_phy_deinit(struct cal_ctx *ctx)
{
int i;
- /* Power down the PHY using the complex IO */
- reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF,
- CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
-
- /* Wait for power down completion */
- for (i = 0; i < 10; i++) {
- if (reg_read_field(ctx->dev,
- CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
- CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
- CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF)
- break;
- usleep_range(1000, 1100);
- }
- ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered Down %s\n",
- ctx->csi2_port,
- reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)),
- (i >= 10) ? "(timeout)" : "");
+ csi2_cio_pwr(ctx, false);
/* Assert Comple IO Reset */
reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),