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From: Hugues Fruchet <hugues.fruchet@foss.st.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Benjamin Mugnier <benjamin.mugnier@foss.st.com>,
Sylvain Petinot <sylvain.petinot@foss.st.com>
CC: <linux-media@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Alain Volmat <alain.volmat@foss.st.com>,
Hugues Fruchet <hugues.fruchet@foss.st.com>
Subject: [PATCH 0/3] MIPID02 pixel clk polarity & serial pixel formats
Date: Mon, 16 May 2022 11:19:31 +0200
Message-ID: <20220516091934.263141-1-hugues.fruchet@foss.st.com>
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| Series |
MIPID02 pixel clk polarity & serial pixel formats
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Message
Hugues Fruchet
May 16, 2022, 9:19 a.m. UTC
Enhance MIPID02 CSI-2 to parallel bridge with pixel clock polarity support and support of 1X16 CSI-2 serial pixel formats. Alain Volmat (1): media: st-mipid02: add support for YVYU and VYUY formats Hugues Fruchet (2): media: st-mipid02: add support of pixel clock polarity media: st-mipid02: expose 1X16 serial pixel format drivers/media/i2c/st-mipid02.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)