Message ID | 20240709135152.185042-9-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers |
Received: from am.mirrors.kernel.org ([147.75.80.249]) by linuxtv.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from <linux-media+bounces-14774-patchwork=linuxtv.org@vger.kernel.org>) id 1sRBH7-0003oo-2l for patchwork@linuxtv.org; Tue, 09 Jul 2024 13:52:58 +0000 Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id AD7F81F22232 for <patchwork@linuxtv.org>; Tue, 9 Jul 2024 13:52:55 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1E308188CB7; Tue, 9 Jul 2024 13:52:52 +0000 (UTC) X-Original-To: linux-media@vger.kernel.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 330BF181D0D; Tue, 9 Jul 2024 13:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720533171; cv=none; b=IABZtozScBSVC/VwS0Z/LyEkCX4umZBRKoE1pIqexPA1INQ4sOPhw3yPjDYo6LBJifJ75FSaaOYwO+vUPngNa64sn3QRtwXkGvWeX1puDE8LSV+BcSjRUJKhPFUp/e2oISHaB7ta0yKXX6iR38XlRjy+9/WSGTg2BRrhpgwH7Gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720533171; c=relaxed/simple; bh=YL9pLO05LtVJrFx2GIztKgltcNq2guFaLtlRrsCbGDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KILd4gfE0JGz7W3yx5pD6iDvcj1M2lmVPKdsQ2xb5S9tM4cM2Q1ySq08RjowBPel0fS6vypZCuNfydfqLuake39LNG7DtxGAZwOvk5BOpNyW9XM6maq6kvk4a2ZW6W8qjwdnuPA58B3ZZu2w5/QEZIpPkxBkGeSX3u06VEFJH/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,195,1716217200"; d="scan'208";a="210808068" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 09 Jul 2024 22:52:49 +0900 Received: from localhost.localdomain (unknown [10.226.92.130]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B391C43DEDAE; Tue, 9 Jul 2024 22:52:43 +0900 (JST) From: Biju Das <biju.das.jz@bp.renesas.com> To: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org> Cc: Biju Das <biju.das.jz@bp.renesas.com>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Mauro Carvalho Chehab <mchehab@kernel.org>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>, Biju Das <biju.das.au@gmail.com> Subject: [PATCH v2 8/9] arm64: dts: renesas: r9a07g043u: Add DU node Date: Tue, 9 Jul 2024 14:51:46 +0100 Message-ID: <20240709135152.185042-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240709135152.185042-1-biju.das.jz@bp.renesas.com> References: <20240709135152.185042-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: <linux-media.vger.kernel.org> List-Subscribe: <mailto:linux-media+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-media+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-LSpam-Score: -1.6 (-) X-LSpam-Report: No, score=-1.6 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DMARC_NONE=0.898,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=no autolearn_force=no |
Series |
Add support for RZ/G2UL Display Unit
|
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Commit Message
Biju Das
July 9, 2024, 1:51 p.m. UTC
Add DU node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 +++++++++++++++++++++
1 file changed, 25 insertions(+)
Comments
Hi Biju, Thank you for the patch. On Tue, Jul 09, 2024 at 02:51:46PM +0100, Biju Das wrote: > Add DU node to RZ/G2UL SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v1->v2: > * No change. > --- > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 +++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > index d88bf23b0782..0a4f24d83791 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > @@ -153,6 +153,31 @@ fcpvd: fcp@10880000 { > resets = <&cpg R9A07G043_LCDC_RESET_N>; > }; > > + du: display@10890000 { > + compatible = "renesas,r9a07g043u-du"; > + reg = <0 0x10890000 0 0x10000>; > + interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; > + clock-names = "aclk", "pclk", "vclk"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G043_LCDC_RESET_N>; > + renesas,vsps = <&vspd 0>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; This may need to change depending on the outcome of the DT bindings discussion. Other than that, Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > + du_out_rgb: endpoint { > + }; > + }; > + }; > + }; > + > irqc: interrupt-controller@110a0000 { > compatible = "renesas,r9a07g043u-irqc", > "renesas,rzg2l-irqc";
Hi Laurent, Thanks for the feedback. > -----Original Message----- > From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Sent: Saturday, July 27, 2024 2:12 AM > Subject: Re: [PATCH v2 8/9] arm64: dts: renesas: r9a07g043u: Add DU node > > Hi Biju, > > Thank you for the patch. > > On Tue, Jul 09, 2024 at 02:51:46PM +0100, Biju Das wrote: > > Add DU node to RZ/G2UL SoC DTSI. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v1->v2: > > * No change. > > --- > > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 > > +++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > index d88bf23b0782..0a4f24d83791 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > @@ -153,6 +153,31 @@ fcpvd: fcp@10880000 { > > resets = <&cpg R9A07G043_LCDC_RESET_N>; > > }; > > > > + du: display@10890000 { > > + compatible = "renesas,r9a07g043u-du"; > > + reg = <0 0x10890000 0 0x10000>; > > + interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, > > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, > > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; > > + clock-names = "aclk", "pclk", "vclk"; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G043_LCDC_RESET_N>; > > + renesas,vsps = <&vspd 0>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@1 { > > + reg = <1>; > > This may need to change depending on the outcome of the DT bindings discussion. Other than that, Agreed. Cheers, Biju > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > + du_out_rgb: endpoint { > > + }; > > + }; > > + }; > > + }; > > + > > irqc: interrupt-controller@110a0000 { > > compatible = "renesas,r9a07g043u-irqc", > > "renesas,rzg2l-irqc"; > > -- > Regards, > > Laurent Pinchart
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index d88bf23b0782..0a4f24d83791 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -153,6 +153,31 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G043_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g043u-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + du_out_rgb: endpoint { + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc";