media: verisilicon: AV1: Correct some registers fields size or position
Commit Message
Some fields aren't well positionned or with incorrect size inside the
hardware registers. Fix them.
That doesn't impact Fluster score test.
Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
.../media/platform/verisilicon/rockchip_vpu981_regs.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
Comments
Le mardi 21 mai 2024 à 17:26 +0200, Benjamin Gaignard a écrit :
> Some fields aren't well positionned or with incorrect size inside the
> hardware registers. Fix them.
>
> That doesn't impact Fluster score test.
Does it impact any known streams though ? (just for a sake of documentation, not
really a problem with your change).
>
> Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> ---
> .../media/platform/verisilicon/rockchip_vpu981_regs.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
> index 182e6c830ff6..990f8e69524a 100644
> --- a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
> +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
> @@ -327,7 +327,7 @@
>
> #define av1_apf_threshold AV1_DEC_REG(55, 0, 0xffff)
> #define av1_apf_single_pu_mode AV1_DEC_REG(55, 30, 0x1)
> -#define av1_apf_disable AV1_DEC_REG(55, 30, 0x1)
> +#define av1_apf_disable AV1_DEC_REG(55, 31, 0x1)
>
> #define av1_dec_max_burst AV1_DEC_REG(58, 0, 0xff)
> #define av1_dec_buswidth AV1_DEC_REG(58, 8, 0x7)
> @@ -337,10 +337,10 @@
> #define av1_dec_mc_polltime AV1_DEC_REG(58, 17, 0x3ff)
> #define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3)
>
> -#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x3f)
> -#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x3f)
> -#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x3f)
> -#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x3f)
> +#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x7f)
> +#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x7f)
> +#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x7f)
> +#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x7f)
> #define av1_ref0_sign_bias AV1_DEC_REG(59, 28, 0x1)
> #define av1_ref1_sign_bias AV1_DEC_REG(59, 29, 0x1)
> #define av1_ref2_sign_bias AV1_DEC_REG(59, 30, 0x1)
Le 31/05/2024 à 14:48, Nicolas Dufresne a écrit :
> Le mardi 21 mai 2024 à 17:26 +0200, Benjamin Gaignard a écrit :
>> Some fields aren't well positionned or with incorrect size inside the
>> hardware registers. Fix them.
>>
>> That doesn't impact Fluster score test.
> Does it impact any known streams though ? (just for a sake of documentation, not
> really a problem with your change).
I have see no impact with the files we currently use or test with fluster.
>
>> Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
>
>> ---
>> .../media/platform/verisilicon/rockchip_vpu981_regs.h | 10 +++++-----
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
>> index 182e6c830ff6..990f8e69524a 100644
>> --- a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
>> +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h
>> @@ -327,7 +327,7 @@
>>
>> #define av1_apf_threshold AV1_DEC_REG(55, 0, 0xffff)
>> #define av1_apf_single_pu_mode AV1_DEC_REG(55, 30, 0x1)
>> -#define av1_apf_disable AV1_DEC_REG(55, 30, 0x1)
>> +#define av1_apf_disable AV1_DEC_REG(55, 31, 0x1)
>>
>> #define av1_dec_max_burst AV1_DEC_REG(58, 0, 0xff)
>> #define av1_dec_buswidth AV1_DEC_REG(58, 8, 0x7)
>> @@ -337,10 +337,10 @@
>> #define av1_dec_mc_polltime AV1_DEC_REG(58, 17, 0x3ff)
>> #define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3)
>>
>> -#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x3f)
>> -#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x3f)
>> -#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x3f)
>> -#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x3f)
>> +#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x7f)
>> +#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x7f)
>> +#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x7f)
>> +#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x7f)
>> #define av1_ref0_sign_bias AV1_DEC_REG(59, 28, 0x1)
>> #define av1_ref1_sign_bias AV1_DEC_REG(59, 29, 0x1)
>> #define av1_ref2_sign_bias AV1_DEC_REG(59, 30, 0x1)
>
@@ -327,7 +327,7 @@
#define av1_apf_threshold AV1_DEC_REG(55, 0, 0xffff)
#define av1_apf_single_pu_mode AV1_DEC_REG(55, 30, 0x1)
-#define av1_apf_disable AV1_DEC_REG(55, 30, 0x1)
+#define av1_apf_disable AV1_DEC_REG(55, 31, 0x1)
#define av1_dec_max_burst AV1_DEC_REG(58, 0, 0xff)
#define av1_dec_buswidth AV1_DEC_REG(58, 8, 0x7)
@@ -337,10 +337,10 @@
#define av1_dec_mc_polltime AV1_DEC_REG(58, 17, 0x3ff)
#define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3)
-#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x3f)
-#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x3f)
-#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x3f)
-#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x3f)
+#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x7f)
+#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x7f)
+#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x7f)
+#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x7f)
#define av1_ref0_sign_bias AV1_DEC_REG(59, 28, 0x1)
#define av1_ref1_sign_bias AV1_DEC_REG(59, 29, 0x1)
#define av1_ref2_sign_bias AV1_DEC_REG(59, 30, 0x1)