On Tue, Aug 09, 2022 at 02:45:08PM +0200, Michael Grzeschik wrote:
>On Thu, Apr 28, 2022 at 12:44:37AM +0200, Nicolas Frattaroli wrote:
>>The RK3566 and RK3568 SoCs come with a small Hantro instance which
>>is solely dedicated to encoding JPEG. This patch adds the necessary
>>structs to the Hantro driver to allow it to function.
>>
>>Tested with the following GStreamer command:
>>
>>gst-launch-1.0 videotestsrc ! v4l2jpegenc ! matroskamux ! \
>> filesink location=foo.mkv
>
>I just tried this pipeline on v5.19. The filesize generated is increasing and
>data is generated. However the content seems to be unusable.
>
>When playing foo.mkv with e.g. vlc the following errors, that no JPEG data was found
>in the images, is generated:
>
>
>[mjpeg @ 0x7f2f08c1f780] No JPEG data found in image
>[mjpeg @ 0x7f2f08c1f780] No JPEG data found in image
>[mjpeg @ 0x7f2f08c1f780] No JPEG data found in image
>...
>
>
>The same with gstreamer:
>
>gst-launch-1.0 filesrc location=foo.mkv ! decodebin ! glimagesink
>../ext/jpeg/gstjpegdec.c(1418): gst_jpeg_dec_handle_frame (): /GstPipeline:pipeline0/GstDecodeBin:decodebin0/GstJpegDec:jpegdec0:
>Decode error #53: Not a JPEG file: starts with 0x00 0x00
>..
>
>
>Do you have an idea why that is? Did you test the pipeline with an earlier
>kernelversion and validated the generated content of foo.mkv?
After further debugging, I found out that my latest port of the bootlin
patches to support h264 encoding broke the hantro driver somehow.
https://git.pengutronix.de/cgit/mgr/linux/log/?h=v5.19/topic/rk3568-vepu-h264-stateless-bootlin
The good news about that is; it is possible that the same issue
was the cause that I thought the h264 encoding is not supported on
the VEPU121. So the support is still unknown
I will come back to that.
Regards,
Michael
@@ -628,6 +628,7 @@ static const struct of_device_id of_hantro_match[] = {
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ { .compatible = "rockchip,rk3568-jpeg-vepu", .data = &rk3568_jpeg_vepu_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
@@ -300,6 +300,7 @@ extern const struct hantro_variant rk3066_vpu_variant;
extern const struct hantro_variant rk3288_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
extern const struct hantro_variant rk3399_vpu_variant;
+extern const struct hantro_variant rk3568_jpeg_vepu_variant;
extern const struct hantro_variant sama5d4_vdec_variant;
extern const struct hantro_variant sunxi_vpu_variant;
@@ -204,6 +204,43 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
},
};
+static const struct hantro_fmt rk3568_jpeg_vepu_enc_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .codec_mode = HANTRO_MODE_NONE,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .codec_mode = HANTRO_MODE_NONE,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .codec_mode = HANTRO_MODE_NONE,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .codec_mode = HANTRO_MODE_NONE,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_JPEG,
+ .codec_mode = HANTRO_MODE_JPEG_ENC,
+ .max_depth = 2,
+ .header_size = JPEG_HEADER_SIZE,
+ .frmsize = {
+ .min_width = 96,
+ .max_width = 8192,
+ .step_width = MB_DIM,
+ .min_height = 32,
+ .max_height = 8192,
+ .step_height = MB_DIM,
+ },
+ },
+};
+
static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
{
struct hantro_dev *vpu = dev_id;
@@ -417,6 +454,14 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
},
};
+static const struct hantro_codec_ops rk3568_jpeg_enc_codec_ops[] = {
+ [HANTRO_MODE_JPEG_ENC] = {
+ .run = rockchip_vpu2_jpeg_enc_run,
+ .reset = rockchip_vpu2_enc_reset,
+ .done = rockchip_vpu2_jpeg_enc_done,
+ },
+};
+
/*
* VPU variant.
*/
@@ -439,6 +484,10 @@ static const struct hantro_irq rockchip_vpu2_irqs[] = {
{ "vdpu", rockchip_vpu2_vdpu_irq },
};
+static const struct hantro_irq rk3568_jpeg_vepu_irqs[] = {
+ { "vepu", rockchip_vpu2_vepu_irq },
+};
+
static const char * const rk3066_vpu_clk_names[] = {
"aclk_vdpu", "hclk_vdpu",
"aclk_vepu", "hclk_vepu"
@@ -545,6 +594,19 @@ const struct hantro_variant rk3399_vpu_variant = {
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
};
+const struct hantro_variant rk3568_jpeg_vepu_variant = {
+ .enc_offset = 0x0,
+ .enc_fmts = rk3568_jpeg_vepu_enc_fmts,
+ .num_enc_fmts = ARRAY_SIZE(rk3568_jpeg_vepu_enc_fmts),
+ .codec = HANTRO_JPEG_ENCODER,
+ .codec_ops = rk3568_jpeg_enc_codec_ops,
+ .irqs = rk3568_jpeg_vepu_irqs,
+ .num_irqs = ARRAY_SIZE(rk3568_jpeg_vepu_irqs),
+ .init = rockchip_vpu_hw_init,
+ .clk_names = rockchip_vpu_clk_names,
+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+};
+
const struct hantro_variant px30_vpu_variant = {
.enc_offset = 0x0,
.enc_fmts = rockchip_vpu_enc_fmts,