@@ -243,6 +243,8 @@ properties:
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).
@@ -337,8 +337,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@1 {
@@ -346,8 +346,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100 {
@@ -355,8 +355,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@101 {
@@ -364,8 +364,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10000 {
@@ -373,8 +373,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10001 {
@@ -382,8 +382,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10100 {
@@ -391,8 +391,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10101 {
@@ -400,8 +400,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
- &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
+ <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100000000 {
@@ -409,8 +409,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x0>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000001 {
@@ -418,8 +418,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x1>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000100 {
@@ -427,8 +427,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000101 {
@@ -436,8 +436,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010000 {
@@ -445,8 +445,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10000>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010001 {
@@ -454,8 +454,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10001>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010100 {
@@ -463,8 +463,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010101 {
@@ -472,8 +472,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
- &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
+ <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
idle-states {
@@ -567,56 +567,56 @@ examples:
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
- cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
+ cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
- cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
+ cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
idle-states {
@@ -66,6 +66,8 @@ properties:
interrupt-affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
When using SPIs, specifies a list of phandles to CPU
nodes corresponding directly to the affinity of
@@ -51,6 +51,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
+ items:
+ minItems: 2
+ maxItems: 2
calxeda,tx-atten:
description: |
@@ -35,7 +35,10 @@ properties:
The SRAM that needs to be claimed to access the display engine
bus.
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to SRAM
+ - description: register value for device
ranges: true
@@ -22,19 +22,28 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the NPE this crypto engine
+ - description: the NPE instance number
description: phandle to the NPE this crypto engine is using, the cell
describing the NPE instance to be used.
queue-rx:
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the RX queue on the NPE
+ - description: the queue instance number
description: phandle to the RX queue on the NPE, the cell describing
the queue instance to be used.
queue-txready:
$ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the TX READY queue on the NPE
+ - description: the queue instance number
description: phandle to the TX READY queue on the NPE, the cell describing
the queue instance to be used.
@@ -69,6 +69,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
+ items:
+ maxItems: 1
description: |
Available display engine frontends (DE 1.0) or mixers (DE
2.0/3.0) available.
@@ -51,7 +51,10 @@ properties:
mediatek,syscon-hdmi:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to system configuration registers
+ - description: register offset in the system configuration registers
description: |
phandle link and register offset to the system configuration registers.
@@ -64,6 +64,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
+ items:
+ maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions.
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
@@ -76,17 +76,21 @@ properties:
renesas,cmms:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ maxItems: 1
description:
A list of phandles to the CMM instances present in the SoC, one for each
available DU channel.
renesas,vsps:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ items:
+ - description: phandle to VSP instance that serves the DU channel
+ - description: Channel index identifying the LIF instance in that VSP
description:
A list of phandle and channel index tuples to the VSPs that handle the
- memory interfaces for the DU channels. The phandle identifies the VSP
- instance that serves the DU channel, and the channel index identifies
- the LIF instance in that VSP.
+ memory interfaces for the DU channels.
required:
- compatible
@@ -21,6 +21,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
Should contain a list of phandles pointing to display interface port
of vop devices. vop definitions as defined in
@@ -45,6 +45,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Should contain a list of phandles pointing to display interface port
of DPU devices.
@@ -88,8 +88,7 @@ properties:
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ $ref: "/schemas/types.yaml#/definitions/phandle"
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
@@ -24,6 +24,8 @@ properties:
dma-masters:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Array of phandles to the DMA controllers the router can direct
the signal to.
@@ -46,7 +46,7 @@ examples:
#dma-cells = <3>;
dma-requests = <128>;
dma-channels = <16>;
- dma-masters = <&dma1 &dma2>;
+ dma-masters = <&dma1>, <&dma2>;
clocks = <&timer_clk>;
};
@@ -43,7 +43,6 @@ properties:
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.
@@ -121,6 +121,8 @@ properties:
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.
@@ -138,6 +138,8 @@ properties:
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
@@ -273,11 +275,11 @@ examples:
ppi-partitions {
part0: interrupt-partition-0 {
- affinity = <&cpu0 &cpu2>;
+ affinity = <&cpu0>, <&cpu2>;
};
part1: interrupt-partition-1 {
- affinity = <&cpu1 &cpu3>;
+ affinity = <&cpu1>, <&cpu3>;
};
};
};
@@ -77,6 +77,8 @@ properties:
ti,unmapped-event-sources:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Array of phandles to DMA controllers where the unmapped events originate.
@@ -101,6 +101,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 32
+ items:
+ maxItems: 1
description: |
List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
@@ -167,8 +169,8 @@ examples:
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb4 &larb5>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
};
@@ -66,6 +66,12 @@ properties:
renesas,ipmmu-main:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to main IPMMU
+ - description: the interrupt bit number associated with the particular
+ cache IPMMU device. The interrupt bit number needs to match the main
+ IPMMU IMSSTR register. Only used by cache IPMMU instances.
description:
Reference to the main IPMMU phandle plus 1 cell. The cell is
the interrupt bit number associated with the particular cache IPMMU
@@ -23,6 +23,8 @@ properties:
leds:
description: A list of LED nodes
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
brightness-levels:
description:
@@ -48,6 +48,10 @@ properties:
allwinner,sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to SRAM
+ - description: register value for device
description: Phandle to the device SRAM
iommus:
@@ -58,11 +58,11 @@ properties:
req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- - description: The 'gpr' is the phandle to general purpose register node.
- - description: The 'req_gpr' is the gpr register offset containing
- CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
- maximum: 0xff
+ - items:
+ - description: The 'gpr' is the phandle to general purpose register node.
+ - description: The 'req_gpr' is the gpr register offset containing
+ CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
+ maximum: 0xff
interconnects:
maxItems: 1
@@ -48,6 +48,10 @@ properties:
ti,camerrx-control:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ - items:
+ - description: phandle to device control module
+ - description: offset to the control_camerarx_core register
description:
phandle to the device control module and offset to the
control_camerarx_core register
@@ -52,7 +52,7 @@ properties:
maxItems: 1
mediatek,smi:
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the smi_common node.
mediatek,larb-id:
@@ -45,6 +45,8 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
minItems: 1
maxItems: 16
+ items:
+ maxItems: 1
description: phandles of the PPMU events used by the controller.
device-handle:
@@ -29,6 +29,10 @@ properties:
allwinner,sram:
description: Phandle to the device SRAM
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to SRAM
+ - description: register value for device
required:
- compatible
@@ -56,10 +56,10 @@ properties:
offset).
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- - description: The phandle to the system control region.
- - description: The register offset.
- - description: The CAN instance number.
+ - items:
+ - description: The phandle to the system control region.
+ - description: The register offset.
+ - description: The CAN instance number.
resets:
maxItems: 1
@@ -84,12 +84,12 @@ properties:
req_bit is the bit offset of CAN stop request.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- - description: The 'gpr' is the phandle to general purpose register node.
- - description: The 'req_gpr' is the gpr register offset of CAN stop request.
- maximum: 0xff
- - description: The 'req_bit' is the bit offset of CAN stop request.
- maximum: 0x1f
+ - items:
+ - description: The 'gpr' is the phandle to general purpose register node.
+ - description: The 'req_gpr' is the gpr register offset of CAN stop request.
+ maximum: 0xff
+ - description: The 'req_bit' is the bit offset of CAN stop request.
+ maximum: 0x1f
fsl,clk-source:
description: |
@@ -34,6 +34,8 @@ properties:
full routing information must be given, not just the one hop
routes to neighbouring switches
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
ethernet:
description:
@@ -158,11 +158,13 @@ properties:
fsl,stop-mode:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to general purpose register node
+ - description: the gpr register offset for ENET stop request
+ - description: the gpr bit offset for ENET stop request
description:
Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
- gpr is the phandle to general purpose register node.
- req_gpr is the gpr register offset for ENET stop request.
- req_bit is the gpr bit offset for ENET stop request.
mdio:
$ref: mdio.yaml#
@@ -29,12 +29,18 @@ properties:
queue-rx:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the RX queue node
+ - description: RX queue instance to use
description: phandle to the RX queue on the NPE
queue-txready:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the TX READY queue node
+ - description: TX READY queue instance to use
description: phandle to the TX READY queue on the NPE
phy-mode: true
@@ -43,7 +49,10 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the NPE this ethernet instance is using
+ - description: the NPE instance to use
description: phandle to the NPE this ethernet instance is using
and the instance to use in the second cell
@@ -25,39 +25,62 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ items:
+ - description: phandle to the NPE this HSS instance is using
+ - description: the NPE instance number
description: phandle to the NPE this HSS instance is using
and the instance to use in the second cell
intel,queue-chl-rxtrig:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the RX trigger queue on the NPE
+ - description: the queue instance number
description: phandle to the RX trigger queue on the NPE
intel,queue-chl-txready:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the TX ready queue on the NPE
+ - description: the queue instance number
description: phandle to the TX ready queue on the NPE
intel,queue-pkt-rx:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the RX queue on the NPE
+ - description: the queue instance number
description: phandle to the packet RX queue on the NPE
intel,queue-pkt-tx:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 4
+ items:
+ items:
+ - description: phandle to the TX queue on the NPE
+ - description: the queue instance number
description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE
intel,queue-pkt-rxfree:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 4
+ items:
+ items:
+ - description: phandle to the RXFREE queue on the NPE
+ - description: the queue instance number
description: phandle to the packet RXFREE0, RXFREE1, RXFREE2 and
RXFREE3 queues on the NPE
intel,queue-pkt-txdone:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
- maxItems: 1
+ items:
+ - items:
+ - description: phandle to the TXDONE queue on the NPE
+ - description: the queue instance number
description: phandle to the packet TXDONE queue on the NPE
cts-gpios:
@@ -54,6 +54,10 @@ properties:
intf_mode:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the GPR syscon
+ - description: the offset of the GPR register
description:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the GPR register, and the offset of the GPR register.
@@ -66,6 +66,10 @@ properties:
socionext,syscon-phy-mode:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to syscon that configures phy mode
+ - description: ID of MAC instance
description:
A phandle to syscon with one argument that configures phy mode.
The argument is the ID of MAC instance.
@@ -74,6 +74,10 @@ properties:
st,syscon:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ - items:
+ - description: phandle to the syscon node which encompases the glue register
+ - description: offset of the control register
description:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the glue register, and the offset of the control register
@@ -136,6 +136,11 @@ properties:
ti,syscon-efuse:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the system control device node which
+ provides access to efuse
+ - description: offset to efuse registers???
description:
Phandle to the system control device node which provides access
to efuse IO range with MAC addresses
@@ -54,6 +54,10 @@ properties:
mediatek,mtd-eeprom:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to MTD partition
+ - description: offset containing EEPROM data
description:
Phandle to a MTD partition + offset containing EEPROM data
@@ -177,6 +177,8 @@ patternProperties:
for the functioning of the current device at the current OPP (where
this property is present).
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
patternProperties:
'^opp-microvolt-':
@@ -35,6 +35,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 12
+ items:
+ maxItems: 1
description: List of phandles for the CPUs connected to this DSU instance.
required:
@@ -47,10 +47,18 @@ properties:
intel,syscfg:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to Chip configuration registers
+ - description: ComboPhy instance id
description: Chip configuration registers handle and ComboPhy instance id
intel,hsio:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to HSIO registers
+ - description: ComboPhy instance id
description: HSIO registers handle and ComboPhy instance id on NOC
intel,aggregation:
@@ -45,6 +45,10 @@ properties:
syscon-phy-power:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the system control module
+ - description: register offset to power on/off the PHY
description:
phandle/offset pair. Phandle to the system control module and
register offset to power on/off the PHY.
@@ -29,6 +29,8 @@ properties:
aspeed,external-nodes:
minItems: 2
maxItems: 2
+ items:
+ maxItems: 1
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
A cell of phandles to external controller nodes:
@@ -39,6 +39,10 @@ properties:
canaan,k210-sysctl-power:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle of the K210 system controller node
+ - description: offset of its power domain control register
description: |
phandle of the K210 system controller node and offset of its
power domain control register.
@@ -44,6 +44,8 @@ properties:
mediatek,pctl-regmap:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
minItems: 1
maxItems: 2
description: |
@@ -41,11 +41,13 @@ properties:
maxItems: 1
st,syscfg:
- description: Should be phandle/offset/mask
- - Phandle to the syscon node which includes IRQ mux selection.
- - The offset of the IRQ mux selection register.
- - The field mask of IRQ mux, needed if different of 0xf.
+ description: Phandle+args to the syscon node which includes IRQ mux selection.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ - items:
+ - description: syscon node which includes IRQ mux selection
+ - description: The offset of the IRQ mux selection register
+ - description: The field mask of IRQ mux, needed if different of 0xf
st,package:
description:
@@ -29,6 +29,8 @@ properties:
domain-idle-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
Phandles of idle states that defines the available states for the
power-domain provider. The idle state definitions are compatible with the
@@ -42,6 +44,8 @@ properties:
operating-points-v2:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
Phandles to the OPP tables of power domains provided by a power domain
provider. If the provider provides a single power domain only or all
@@ -35,6 +35,8 @@ properties:
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
Array of phandles pointing to CPU cores, which should match the order of
CPU cores used by the WUPCR and PSTR registers in the Advanced Power
@@ -129,6 +129,8 @@ $defs:
pm_qos:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
A number of phandles to qos blocks which need to be saved and restored
while power domain switches state.
@@ -14,6 +14,9 @@ description: |
phandle in monitored-battery. If specified the driver uses the
charge-full-design-microamp-hours property of the battery.
+allOf:
+ - $ref: power-supply.yaml#
+
properties:
compatible:
const: cellwise,cw2015
@@ -37,9 +40,6 @@ properties:
minimum: 250
power-supplies:
- description:
- Specifies supplies used for charging the battery connected to this gauge
- $ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8 # Should be enough
@@ -12,6 +12,8 @@ maintainers:
properties:
power-supplies:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
This property is added to a supply in order to list the devices which
supply it power, referenced by their phandles.
@@ -213,6 +213,8 @@ properties:
is 2-way - all coupled regulators should be linked with each other.
A regulator should not be coupled with its supplier.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ maxItems: 1
regulator-coupled-max-spread:
description: Array of maximum spread between voltages of coupled regulators
@@ -23,7 +23,7 @@ properties:
- st,stm32mp1-booster
st,syscfg:
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: "/schemas/types.yaml#/definitions/phandle"
description: phandle to system configuration controller.
vdda-supply:
@@ -115,6 +115,12 @@ properties:
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle reference to a syscon representing TCSR
+ - description: offsets within syscon for q6 halt registers
+ - description: offsets within syscon for modem halt registers
+ - description: offsets within syscon for nc halt registers
description:
Phandle reference to a syscon representing TCSR followed by the
three offsets within syscon for q6, modem and nc halt registers.
@@ -29,17 +29,22 @@ properties:
st,syscfg-holdboot:
description: remote processor reset hold boot
- - Phandle of syscon block.
- - The offset of the hold boot setting register.
- - The field mask of the hold boot.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ items:
+ - items:
+ - description: Phandle of syscon block
+ - description: The offset of the hold boot setting register
+ - description: The field mask of the hold boot
st,syscfg-tz:
description:
Reference to the system configuration which holds the RCC trust zone mode
$ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ items:
+ - items:
+ - description: Phandle of syscon block
+ - description: FIXME
+ - description: FIXME
interrupts:
description: Should contain the WWDG1 watchdog reset interrupt
@@ -93,20 +98,32 @@ properties:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description: |
Reference to the system configuration which holds the remote
- maxItems: 1
+ items:
+ - items:
+ - description: Phandle of syscon block
+ - description: FIXME
+ - description: FIXME
st,syscfg-m4-state:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description: |
Reference to the tamp register which exposes the Cortex-M4 state.
- maxItems: 1
+ items:
+ - items:
+ - description: Phandle of syscon block with the tamp register
+ - description: FIXME
+ - description: FIXME
st,syscfg-rsc-tbl:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description: |
Reference to the tamp register which references the Cortex-M4
resource table address.
- maxItems: 1
+ items:
+ - items:
+ - description: Phandle of syscon block with the tamp register
+ - description: FIXME
+ - description: FIXME
st,auto-boot:
$ref: /schemas/types.yaml#/definitions/flag
@@ -79,6 +79,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
+ items:
+ maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions. The regions
should be defined as child nodes of the respective SRAM node, and
@@ -189,6 +189,8 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
+ items:
+ maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions. The regions
should be defined as child nodes of the respective SRAM node, and
@@ -123,13 +123,14 @@ properties:
ti,bootreg:
$ref: /schemas/types.yaml#/definitions/phandle-array
- description: |
- Should be a triple of the phandle to the System Control
- Configuration region that contains the boot address
- register, the register offset of the boot address
- register within the System Control module, and the bit
- shift within the register. This property is required for
- all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs.
+ items:
+ - items:
+ - description: phandle to the System Control Configuration region
+ - description: register offset of the boot address register
+ - description: the bit shift within the register
+ description:
+ This property is required for all the DSP instances on OMAP4, OMAP5
+ and DRA7xx SoCs.
ti,autosuspend-delay-ms:
description: |
@@ -140,6 +141,8 @@ properties:
ti,timers:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
One or more phandles to OMAP DMTimer nodes, that serve
as System/Tick timers for the OS running on the remote
@@ -156,6 +159,8 @@ properties:
ti,watchdog-timers:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
One or more phandles to OMAP DMTimer nodes, used to
serve as Watchdog timers for the processor cores. This
@@ -48,6 +48,10 @@ properties:
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register syscon node
+ - description: offset of SW_CONF register for this USI controller
description:
Should be phandle/offset pair. The phandle to System Register syscon node
(for the same domain where this USI controller resides) and the offset
@@ -27,6 +27,8 @@ properties:
sound-dai:
minItems: 2
maxItems: 2
+ items:
+ maxItems: 1
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
phandles to the I2S controller and bluetooth codec,
@@ -21,8 +21,7 @@ properties:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the I2S controller
required:
- sound-dai
@@ -102,9 +102,11 @@ patternProperties:
By default SAI sub-block is in asynchronous mode.
Must contain the phandle and index of the SAI sub-block providing
the synchronization.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/phandle-array
- - maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle of the SAI sub-block
+ - description: index of the SAI sub-block
st,iec60958:
description:
@@ -66,9 +66,9 @@ examples:
compatible = "qcom,kryo385";
reg = <0x0 0x0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0>,
+ <&LITTLE_CPU_SLEEP_1>,
+ <&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -37,8 +37,8 @@ properties:
exit-latency-us:
description: |
- The exit latency constraint in microsecond for the injected idle state
- for the device. It is the latency constraint to apply when selecting an
+ The exit latency constraint in microsecond for the injected idle state
+ for the device. It is the latency constraint to apply when selecting an
idle state from among all the present ones.
required:
@@ -65,7 +65,7 @@ examples:
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <436>;
#cooling-cells = <2>; /* min followed by max */
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
@@ -81,7 +81,7 @@ examples:
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <436>;
#cooling-cells = <2>; /* min followed by max */
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
@@ -83,7 +83,7 @@ properties:
- const: ss
nvidia,xusb-padctl:
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the XUSB pad controller that is used to configure the USB pads
used by the XUDC controller.