[v3,10/10] arm64: dts: rockchip: Add VPU support for the PX30
Commit Message
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.
Describe these two entities in device-tree.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
Comments
On 2021-07-19 21:52, Ezequiel Garcia wrote:
> From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
>
> The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.
> Describe these two entities in device-tree.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/px30.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> index 248ebb61aa79..05ce8ce5e4be 100644
> --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> @@ -1024,6 +1024,29 @@ gpu: gpu@ff400000 {
> status = "disabled";
> };
>
> + vpu: video-codec@ff442000 {
> + compatible = "rockchip,px30-vpu";
> + reg = <0x0 0xff442000 0x0 0x800>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "vepu", "vdpu";
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + clock-names = "aclk", "hclk";
> + iommus = <&vpu_mmu>;
> + power-domains = <&power PX30_PD_VPU>;
> + };
> +
> + vpu_mmu: iommu@ff442800 {
> + compatible = "rockchip,iommu";
> + reg = <0x0 0xff442800 0x0 0x100>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "vpu_mmu";
Nit: "interrupt-names" is not part of the IOMMU binding. Same for the
RK3568 patch too ;)
Robin.
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + clock-names = "aclk", "iface";
> + #iommu-cells = <0>;
> + power-domains = <&power PX30_PD_VPU>;
> + };
> +
> dsi: dsi@ff450000 {
> compatible = "rockchip,px30-mipi-dsi";
> reg = <0x0 0xff450000 0x0 0x10000>;
>
@@ -1024,6 +1024,29 @@ gpu: gpu@ff400000 {
status = "disabled";
};
+ vpu: video-codec@ff442000 {
+ compatible = "rockchip,px30-vpu";
+ reg = <0x0 0xff442000 0x0 0x800>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@ff442800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff442800 0x0 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;