[v9,08/10] gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till calibration done
Message ID | 1596740494-19306-9-git-send-email-skomatineni@nvidia.com (mailing list archive) |
---|---|
State | Superseded, archived |
Delegated to: | Hans Verkuil |
Headers |
Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from <linux-media-owner@vger.kernel.org>) id 1k3l4Y-00Aazn-Tp; Thu, 06 Aug 2020 18:57:04 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729684AbgHFTCQ (ORCPT <rfc822;mkrufky@linuxtv.org> + 1 other); Thu, 6 Aug 2020 15:02:16 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:11917 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729193AbgHFTBp (ORCPT <rfc822;linux-media@vger.kernel.org>); Thu, 6 Aug 2020 15:01:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5f2c538b0000>; Thu, 06 Aug 2020 12:01:31 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 06 Aug 2020 12:01:44 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Aug 2020 12:01:44 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 6 Aug 2020 19:01:44 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 6 Aug 2020 19:01:43 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.190]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id <B5f2c53960002>; Thu, 06 Aug 2020 12:01:43 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>, <sakari.ailus@iki.fi>, <robh+dt@kernel.org>, <helen.koike@collabora.com> CC: <digetx@gmail.com>, <gregkh@linuxfoundation.org>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till calibration done Date: Thu, 6 Aug 2020 12:01:32 -0700 Message-ID: <1596740494-19306-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com> References: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596740491; bh=LTS932fdLvwXI9om1DiK7LN0NCuI1nrSF4ze3h9IP80=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JUTR1VQx+mSyXYtJ+ORG/ZfpDlmkPyEM1o1CVjWhBPYzQ3Q5sltU50l7o1cIds63l KDvPnFngDb996vl4UkRwV0EmWer06cyCTohvqw6kviQoi7rq9tXxbZAnyQM2W/K3Qu iUy0XE/XKiAt8lLpsWDdgiAMaeQA7APymgK5gMrAvm20U1UR9eXes45oQPeBVV7cIe cb7scIrHGb+u84Uz7uMR+AjenKdM6GQR7gp47wUG5Qc/kwzdLVw8pWOcI8jY1O9MYz oyQcY7+8KbGX1FrosUsiPbmw/eVr9tbbQdnJNsH4lQ0n/1UNLms0SiOvv+fZsK05SK +EFw5DCEyDQpA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: <linux-media.vger.kernel.org> X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no |
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Support for Tegra video capture from external sensor
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Commit Message
Sowjanya Komatineni
Aug. 6, 2020, 7:01 p.m. UTC
With the split of MIPI calibration into tegra_mipi_calibrate() and tegra_mipi_wait(), MIPI clock is not kept enabled and mutex is not locked till the calibration is done. So, this patch keeps MIPI clock enabled and mutex locked after triggering start of calibration till its done. To let calibration process go through its finite sequence codes before calibration logic waiting for pads idle state added wait time of 75usec to make sure it sees idle state to apply the results. This patch renames tegra_mipi_calibrate() as tegra_mipi_start_calibration() and tegra_mipi_wait() as tegra_mipi_finish_calibration() to be inline with their usage. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/gpu/drm/tegra/dsi.c | 4 ++-- drivers/gpu/host1x/mipi.c | 22 ++++++++++------------ include/linux/host1x.h | 4 ++-- 3 files changed, 14 insertions(+), 16 deletions(-)
Comments
06.08.2020 22:01, Sowjanya Komatineni пишет: ... > +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) > { > const struct tegra_mipi_soc *soc = device->mipi->soc; > unsigned int i; > @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) > value |= MIPI_CAL_CTRL_START; > tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); > > - mutex_unlock(&device->mipi->lock); > - clk_disable(device->mipi->clk); > + /* > + * Wait for min 72uS to let calibration logic finish calibration > + * sequence codes before waiting for pads idle state to apply the > + * results. > + */ > + usleep_range(75, 80); Could you please explain why the ACTIVE bit can't be polled instead of using the fixed delay? Doesn't ACTIVE bit represents the state of the busy FSM?
On 8/6/20 7:31 PM, Dmitry Osipenko wrote: > 06.08.2020 22:01, Sowjanya Komatineni пишет: > ... >> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >> { >> const struct tegra_mipi_soc *soc = device->mipi->soc; >> unsigned int i; >> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) >> value |= MIPI_CAL_CTRL_START; >> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >> >> - mutex_unlock(&device->mipi->lock); >> - clk_disable(device->mipi->clk); >> + /* >> + * Wait for min 72uS to let calibration logic finish calibration >> + * sequence codes before waiting for pads idle state to apply the >> + * results. >> + */ >> + usleep_range(75, 80); > Could you please explain why the ACTIVE bit can't be polled instead of > using the fixed delay? Doesn't ACTIVE bit represents the state of the > busy FSM? Based on internal discussion, ACTIVE bit gets cleared when all enabled pads calibration is done (same time as when DONE set to 1). Will request HW designer to look into design and confirm exactly when ACTIVE bit gets cleared. Will get back on this.
On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: > > On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >> 06.08.2020 22:01, Sowjanya Komatineni пишет: >> ... >>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>> { >>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>> unsigned int i; >>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>> tegra_mipi_device *device) >>> value |= MIPI_CAL_CTRL_START; >>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>> - mutex_unlock(&device->mipi->lock); >>> - clk_disable(device->mipi->clk); >>> + /* >>> + * Wait for min 72uS to let calibration logic finish calibration >>> + * sequence codes before waiting for pads idle state to apply the >>> + * results. >>> + */ >>> + usleep_range(75, 80); >> Could you please explain why the ACTIVE bit can't be polled instead of >> using the fixed delay? Doesn't ACTIVE bit represents the state of the >> busy FSM? > > Based on internal discussion, ACTIVE bit gets cleared when all enabled > pads calibration is done (same time as when DONE set to 1). > > Will request HW designer to look into design and confirm exactly when > ACTIVE bit gets cleared. > > Will get back on this. > Verified with HW designer. above is correct. ACTIVE bit update happens same time as DONE bit. Active = !(DONE) In case of calibration logic waiting for LP-11 where done bit does not get set, ACTIVE will still be 1 and on next start trigger new calibration will start > >
On 8/6/20 8:14 PM, Sowjanya Komatineni wrote: > > On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: >> >> On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >>> 06.08.2020 22:01, Sowjanya Komatineni пишет: >>> ... >>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>>> { >>>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>>> unsigned int i; >>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>>> tegra_mipi_device *device) >>>> value |= MIPI_CAL_CTRL_START; >>>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>> - mutex_unlock(&device->mipi->lock); >>>> - clk_disable(device->mipi->clk); >>>> + /* >>>> + * Wait for min 72uS to let calibration logic finish calibration >>>> + * sequence codes before waiting for pads idle state to apply the >>>> + * results. >>>> + */ >>>> + usleep_range(75, 80); >>> Could you please explain why the ACTIVE bit can't be polled instead of >>> using the fixed delay? Doesn't ACTIVE bit represents the state of the >>> busy FSM? >> >> Based on internal discussion, ACTIVE bit gets cleared when all >> enabled pads calibration is done (same time as when DONE set to 1). >> >> Will request HW designer to look into design and confirm exactly when >> ACTIVE bit gets cleared. >> >> Will get back on this. >> > Verified with HW designer. above is correct. ACTIVE bit update happens > same time as DONE bit. > > Active = !(DONE) > > In case of calibration logic waiting for LP-11 where done bit does not > get set, ACTIVE will still be 1 and on next start trigger new > calibration will start > Based on internal design check from designer, as long as its in waiting for LP-11 stage, next calibration request can be triggered again but ACTIVE bit we will see it at 1. So we should check for DONE bits to confirm if calibration is done or not. To start next calibration, it can take effect as long as its in wait for LP-11 mode. >> >>
07.08.2020 06:18, Sowjanya Komatineni пишет: > > On 8/6/20 8:14 PM, Sowjanya Komatineni wrote: >> >> On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: >>> >>> On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >>>> 06.08.2020 22:01, Sowjanya Komatineni пишет: >>>> ... >>>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>>>> { >>>>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>>>> unsigned int i; >>>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>>>> tegra_mipi_device *device) >>>>> value |= MIPI_CAL_CTRL_START; >>>>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>>> - mutex_unlock(&device->mipi->lock); >>>>> - clk_disable(device->mipi->clk); >>>>> + /* >>>>> + * Wait for min 72uS to let calibration logic finish calibration >>>>> + * sequence codes before waiting for pads idle state to apply the >>>>> + * results. >>>>> + */ >>>>> + usleep_range(75, 80); >>>> Could you please explain why the ACTIVE bit can't be polled instead of >>>> using the fixed delay? Doesn't ACTIVE bit represents the state of the >>>> busy FSM? >>> >>> Based on internal discussion, ACTIVE bit gets cleared when all >>> enabled pads calibration is done (same time as when DONE set to 1). >>> >>> Will request HW designer to look into design and confirm exactly when >>> ACTIVE bit gets cleared. >>> >>> Will get back on this. >>> >> Verified with HW designer. above is correct. ACTIVE bit update happens >> same time as DONE bit. >> >> Active = !(DONE) >> >> In case of calibration logic waiting for LP-11 where done bit does not >> get set, ACTIVE will still be 1 and on next start trigger new >> calibration will start >> > Based on internal design check from designer, as long as its in waiting > for LP-11 stage, next calibration request can be triggered again but > ACTIVE bit we will see it at 1. So we should check for DONE bits to > confirm if calibration is done or not. > > To start next calibration, it can take effect as long as its in wait for > LP-11 mode. I meant the start_calibration() will poll the ACTIVE bit (calibration busy), while the finish_calibration() will poll the DONE bit (calibration applied).
On 8/6/20 9:01 PM, Dmitry Osipenko wrote: > 07.08.2020 06:18, Sowjanya Komatineni пишет: >> On 8/6/20 8:14 PM, Sowjanya Komatineni wrote: >>> On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: >>>> On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >>>>> 06.08.2020 22:01, Sowjanya Komatineni пишет: >>>>> ... >>>>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>>>>> { >>>>>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>>>>> unsigned int i; >>>>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>>>>> tegra_mipi_device *device) >>>>>> value |= MIPI_CAL_CTRL_START; >>>>>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>>>> - mutex_unlock(&device->mipi->lock); >>>>>> - clk_disable(device->mipi->clk); >>>>>> + /* >>>>>> + * Wait for min 72uS to let calibration logic finish calibration >>>>>> + * sequence codes before waiting for pads idle state to apply the >>>>>> + * results. >>>>>> + */ >>>>>> + usleep_range(75, 80); >>>>> Could you please explain why the ACTIVE bit can't be polled instead of >>>>> using the fixed delay? Doesn't ACTIVE bit represents the state of the >>>>> busy FSM? >>>> Based on internal discussion, ACTIVE bit gets cleared when all >>>> enabled pads calibration is done (same time as when DONE set to 1). >>>> >>>> Will request HW designer to look into design and confirm exactly when >>>> ACTIVE bit gets cleared. >>>> >>>> Will get back on this. >>>> >>> Verified with HW designer. above is correct. ACTIVE bit update happens >>> same time as DONE bit. >>> >>> Active = !(DONE) >>> >>> In case of calibration logic waiting for LP-11 where done bit does not >>> get set, ACTIVE will still be 1 and on next start trigger new >>> calibration will start >>> >> Based on internal design check from designer, as long as its in waiting >> for LP-11 stage, next calibration request can be triggered again but >> ACTIVE bit we will see it at 1. So we should check for DONE bits to >> confirm if calibration is done or not. >> >> To start next calibration, it can take effect as long as its in wait for >> LP-11 mode. > I meant the start_calibration() will poll the ACTIVE bit (calibration > busy), while the finish_calibration() will poll the DONE bit > (calibration applied). ACTIVE bit can be 1 when previous calibration process does not see LP-11. So there is no need to use ACTIVE bit during start of calibration. At HW level, both ACTIVE and DONE bits get set at same time. So waiting for ACTIVE to be 0 during start calibration instead of 7uS will not work as ACTIVE bit will not become 0 after calibration sequence codes and it will get updated along with DONE bits only after applying results to pads which happens after seeing LP-11 on pads.
On 8/6/20 9:05 PM, Sowjanya Komatineni wrote: > > On 8/6/20 9:01 PM, Dmitry Osipenko wrote: >> 07.08.2020 06:18, Sowjanya Komatineni пишет: >>> On 8/6/20 8:14 PM, Sowjanya Komatineni wrote: >>>> On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: >>>>> On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >>>>>> 06.08.2020 22:01, Sowjanya Komatineni пишет: >>>>>> ... >>>>>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>>>>>> { >>>>>>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>>>>>> unsigned int i; >>>>>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>>>>>> tegra_mipi_device *device) >>>>>>> value |= MIPI_CAL_CTRL_START; >>>>>>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>>>>> - mutex_unlock(&device->mipi->lock); >>>>>>> - clk_disable(device->mipi->clk); >>>>>>> + /* >>>>>>> + * Wait for min 72uS to let calibration logic finish >>>>>>> calibration >>>>>>> + * sequence codes before waiting for pads idle state to >>>>>>> apply the >>>>>>> + * results. >>>>>>> + */ >>>>>>> + usleep_range(75, 80); >>>>>> Could you please explain why the ACTIVE bit can't be polled >>>>>> instead of >>>>>> using the fixed delay? Doesn't ACTIVE bit represents the state of >>>>>> the >>>>>> busy FSM? >>>>> Based on internal discussion, ACTIVE bit gets cleared when all >>>>> enabled pads calibration is done (same time as when DONE set to 1). >>>>> >>>>> Will request HW designer to look into design and confirm exactly when >>>>> ACTIVE bit gets cleared. >>>>> >>>>> Will get back on this. >>>>> >>>> Verified with HW designer. above is correct. ACTIVE bit update happens >>>> same time as DONE bit. >>>> >>>> Active = !(DONE) >>>> >>>> In case of calibration logic waiting for LP-11 where done bit does not >>>> get set, ACTIVE will still be 1 and on next start trigger new >>>> calibration will start >>>> >>> Based on internal design check from designer, as long as its in waiting >>> for LP-11 stage, next calibration request can be triggered again but >>> ACTIVE bit we will see it at 1. So we should check for DONE bits to >>> confirm if calibration is done or not. >>> >>> To start next calibration, it can take effect as long as its in wait >>> for >>> LP-11 mode. >> I meant the start_calibration() will poll the ACTIVE bit (calibration >> busy), while the finish_calibration() will poll the DONE bit >> (calibration applied). > > ACTIVE bit can be 1 when previous calibration process does not see LP-11. > > So there is no need to use ACTIVE bit during start of calibration. > > At HW level, both ACTIVE and DONE bits get set at same time. > > So waiting for ACTIVE to be 0 during start calibration instead of > *75uS will not work as ACTIVE bit will not become 0 after calibration > sequence codes and it will get updated along with DONE bits only after > applying results to pads which happens after seeing LP-11 on pads. > *typo fixed
07.08.2020 07:06, Sowjanya Komatineni пишет: > > On 8/6/20 9:05 PM, Sowjanya Komatineni wrote: >> >> On 8/6/20 9:01 PM, Dmitry Osipenko wrote: >>> 07.08.2020 06:18, Sowjanya Komatineni пишет: >>>> On 8/6/20 8:14 PM, Sowjanya Komatineni wrote: >>>>> On 8/6/20 8:10 PM, Sowjanya Komatineni wrote: >>>>>> On 8/6/20 7:31 PM, Dmitry Osipenko wrote: >>>>>>> 06.08.2020 22:01, Sowjanya Komatineni пишет: >>>>>>> ... >>>>>>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) >>>>>>>> { >>>>>>>> const struct tegra_mipi_soc *soc = device->mipi->soc; >>>>>>>> unsigned int i; >>>>>>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct >>>>>>>> tegra_mipi_device *device) >>>>>>>> value |= MIPI_CAL_CTRL_START; >>>>>>>> tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>>>>>> - mutex_unlock(&device->mipi->lock); >>>>>>>> - clk_disable(device->mipi->clk); >>>>>>>> + /* >>>>>>>> + * Wait for min 72uS to let calibration logic finish >>>>>>>> calibration >>>>>>>> + * sequence codes before waiting for pads idle state to >>>>>>>> apply the >>>>>>>> + * results. >>>>>>>> + */ >>>>>>>> + usleep_range(75, 80); >>>>>>> Could you please explain why the ACTIVE bit can't be polled >>>>>>> instead of >>>>>>> using the fixed delay? Doesn't ACTIVE bit represents the state of >>>>>>> the >>>>>>> busy FSM? >>>>>> Based on internal discussion, ACTIVE bit gets cleared when all >>>>>> enabled pads calibration is done (same time as when DONE set to 1). >>>>>> >>>>>> Will request HW designer to look into design and confirm exactly when >>>>>> ACTIVE bit gets cleared. >>>>>> >>>>>> Will get back on this. >>>>>> >>>>> Verified with HW designer. above is correct. ACTIVE bit update happens >>>>> same time as DONE bit. >>>>> >>>>> Active = !(DONE) >>>>> >>>>> In case of calibration logic waiting for LP-11 where done bit does not >>>>> get set, ACTIVE will still be 1 and on next start trigger new >>>>> calibration will start >>>>> >>>> Based on internal design check from designer, as long as its in waiting >>>> for LP-11 stage, next calibration request can be triggered again but >>>> ACTIVE bit we will see it at 1. So we should check for DONE bits to >>>> confirm if calibration is done or not. >>>> >>>> To start next calibration, it can take effect as long as its in wait >>>> for >>>> LP-11 mode. >>> I meant the start_calibration() will poll the ACTIVE bit (calibration >>> busy), while the finish_calibration() will poll the DONE bit >>> (calibration applied). >> >> ACTIVE bit can be 1 when previous calibration process does not see LP-11. >> >> So there is no need to use ACTIVE bit during start of calibration. >> >> At HW level, both ACTIVE and DONE bits get set at same time. >> >> So waiting for ACTIVE to be 0 during start calibration instead of >> *75uS will not work as ACTIVE bit will not become 0 after calibration >> sequence codes and it will get updated along with DONE bits only after >> applying results to pads which happens after seeing LP-11 on pads. >> > *typo fixed I see now, thank you.
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 3820e8d..a7864e9 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -694,11 +694,11 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err = tegra_mipi_calibrate(dsi->mipi); + err = tegra_mipi_start_calibration(dsi->mipi); if (err < 0) return err; - return tegra_mipi_wait(dsi->mipi); + return tegra_mipi_finish_calibration(dsi->mipi); } static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e606464..2efe12d 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -293,19 +293,13 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) } EXPORT_SYMBOL(tegra_mipi_disable); -int tegra_mipi_wait(struct tegra_mipi_device *device) +int tegra_mipi_finish_calibration(struct tegra_mipi_device *device) { struct tegra_mipi *mipi = device->mipi; void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2); u32 value; int err; - err = clk_enable(device->mipi->clk); - if (err < 0) - return err; - - mutex_lock(&device->mipi->lock); - err = readl_relaxed_poll_timeout(status_reg, value, !(value & MIPI_CAL_STATUS_ACTIVE) && (value & MIPI_CAL_STATUS_DONE), 50, @@ -315,9 +309,9 @@ int tegra_mipi_wait(struct tegra_mipi_device *device) return err; } -EXPORT_SYMBOL(tegra_mipi_wait); +EXPORT_SYMBOL(tegra_mipi_finish_calibration); -int tegra_mipi_calibrate(struct tegra_mipi_device *device) +int tegra_mipi_start_calibration(struct tegra_mipi_device *device) { const struct tegra_mipi_soc *soc = device->mipi->soc; unsigned int i; @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) value |= MIPI_CAL_CTRL_START; tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); - mutex_unlock(&device->mipi->lock); - clk_disable(device->mipi->clk); + /* + * Wait for min 72uS to let calibration logic finish calibration + * sequence codes before waiting for pads idle state to apply the + * results. + */ + usleep_range(75, 80); return 0; } -EXPORT_SYMBOL(tegra_mipi_calibrate); +EXPORT_SYMBOL(tegra_mipi_start_calibration); static const struct tegra_mipi_pad tegra114_mipi_pads[] = { { .data = MIPI_CAL_CONFIG_CSIA }, diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 20c885d..ce59a6a 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -333,7 +333,7 @@ struct tegra_mipi_device *tegra_mipi_request(struct device *device, void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); -int tegra_mipi_calibrate(struct tegra_mipi_device *device); -int tegra_mipi_wait(struct tegra_mipi_device *device); +int tegra_mipi_start_calibration(struct tegra_mipi_device *device); +int tegra_mipi_finish_calibration(struct tegra_mipi_device *device); #endif