diff mbox series

[14/16] media: ti-vpe: cal: improve wait for CIO resetdone

Message ID 20200313114121.32182-14-tomi.valkeinen@ti.com (mailing list archive)
State Changes Requested, archived
Delegated to: Hans Verkuil
Headers
Series [01/16] media: ti-vpe: cal: fix use of wrong macro |

Commit Message

Tomi Valkeinen March 13, 2020, 11:41 a.m. UTC 
  Sometimes waiting for ComplexIO resetdone timeouts. Testing shows that
sometimes we need to wait more than what the current code does. It is
not clear how long this wait can be, but it is based on how quickly the
sensor provides a valid clock, and how quickly CAL syncs to it.

Change the code to make it more obvious how long we'll wait, and set a
wider range for usleep_range. Increase the timeout to 750ms.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/media/platform/ti-vpe/cal.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

Comments

Hans Verkuil March 16, 2020, 10:05 a.m. UTC | #1 
On 3/13/20 12:41 PM, Tomi Valkeinen wrote:
> Sometimes waiting for ComplexIO resetdone timeouts. 

This sentence is hard to read. You probably mean:

Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'.

Regards,

	Hans

Testing shows that
> sometimes we need to wait more than what the current code does. It is
> not clear how long this wait can be, but it is based on how quickly the
> sensor provides a valid clock, and how quickly CAL syncs to it.
> 
> Change the code to make it more obvious how long we'll wait, and set a
> wider range for usleep_range. Increase the timeout to 750ms.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>  drivers/media/platform/ti-vpe/cal.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index 319312770eea..929f9b3ca4f9 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -824,20 +824,21 @@ static void csi2_phy_init(struct cal_ctx *ctx)
>  
>  static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
>  {
> -	int i;
> +	unsigned long timeout;
>  
> -	for (i = 0; i < 250; i++) {
> +	timeout = jiffies + msecs_to_jiffies(750);
> +	while (time_before(jiffies, timeout)) {
>  		if (reg_read_field(ctx->dev,
>  				   CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
>  				   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
>  		    CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
>  			break;
> -		usleep_range(1000, 1100);
> +		usleep_range(500, 5000);
>  	}
> -	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n",
> +
> +	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done\n",
>  		ctx->csi2_port,
> -		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i,
> -		(i >= 250) ? "(timeout)" : "");
> +		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
>  
>  	if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
>  			   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
>
Tomi Valkeinen March 16, 2020, 10:11 a.m. UTC | #2 
On 16/03/2020 12:05, Hans Verkuil wrote:
> On 3/13/20 12:41 PM, Tomi Valkeinen wrote:
>> Sometimes waiting for ComplexIO resetdone timeouts.
> 
> This sentence is hard to read. You probably mean:
> 
> Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'.

Ah, indeed, it's confusing. And same with the next patch. I'll update the desc.

  Tomi
Laurent Pinchart March 16, 2020, 12:43 p.m. UTC | #3 
Hi Tomi,

Thank you for the patch.

On Fri, Mar 13, 2020 at 01:41:19PM +0200, Tomi Valkeinen wrote:
> Sometimes waiting for ComplexIO resetdone timeouts. Testing shows that
> sometimes we need to wait more than what the current code does. It is
> not clear how long this wait can be, but it is based on how quickly the
> sensor provides a valid clock, and how quickly CAL syncs to it.
> 
> Change the code to make it more obvious how long we'll wait, and set a
> wider range for usleep_range. Increase the timeout to 750ms.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>  drivers/media/platform/ti-vpe/cal.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index 319312770eea..929f9b3ca4f9 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -824,20 +824,21 @@ static void csi2_phy_init(struct cal_ctx *ctx)
>  
>  static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
>  {
> -	int i;
> +	unsigned long timeout;
>  
> -	for (i = 0; i < 250; i++) {
> +	timeout = jiffies + msecs_to_jiffies(750);
> +	while (time_before(jiffies, timeout)) {
>  		if (reg_read_field(ctx->dev,
>  				   CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
>  				   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
>  		    CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
>  			break;
> -		usleep_range(1000, 1100);
> +		usleep_range(500, 5000);
>  	}

How about using readx_poll_timeout() ?

> -	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n",
> +
> +	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done\n",
>  		ctx->csi2_port,
> -		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i,
> -		(i >= 250) ? "(timeout)" : "");
> +		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
>  
>  	if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
>  			   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
Tomi Valkeinen March 17, 2020, 11:34 a.m. UTC | #4 
On 16/03/2020 14:43, Laurent Pinchart wrote:
> Hi Tomi,
> 
> Thank you for the patch.
> 
> On Fri, Mar 13, 2020 at 01:41:19PM +0200, Tomi Valkeinen wrote:
>> Sometimes waiting for ComplexIO resetdone timeouts. Testing shows that
>> sometimes we need to wait more than what the current code does. It is
>> not clear how long this wait can be, but it is based on how quickly the
>> sensor provides a valid clock, and how quickly CAL syncs to it.
>>
>> Change the code to make it more obvious how long we'll wait, and set a
>> wider range for usleep_range. Increase the timeout to 750ms.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> ---
>>   drivers/media/platform/ti-vpe/cal.c | 13 +++++++------
>>   1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
>> index 319312770eea..929f9b3ca4f9 100644
>> --- a/drivers/media/platform/ti-vpe/cal.c
>> +++ b/drivers/media/platform/ti-vpe/cal.c
>> @@ -824,20 +824,21 @@ static void csi2_phy_init(struct cal_ctx *ctx)
>>   
>>   static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
>>   {
>> -	int i;
>> +	unsigned long timeout;
>>   
>> -	for (i = 0; i < 250; i++) {
>> +	timeout = jiffies + msecs_to_jiffies(750);
>> +	while (time_before(jiffies, timeout)) {
>>   		if (reg_read_field(ctx->dev,
>>   				   CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
>>   				   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
>>   		    CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
>>   			break;
>> -		usleep_range(1000, 1100);
>> +		usleep_range(500, 5000);
>>   	}
> 
> How about using readx_poll_timeout() ?

There's no function that directly fits readx_poll_timeout's accessor function, so I think using 
readl_poll_timeout and calculating the address manually would be the way to use *_poll_timeout.

But it does skip the register access functions the driver uses (reg_read/write).

So... It would be nice to use *_poll_timeout, but I'm not sure if it worth breaking the register 
access model the driver uses.

  Tomi
diff mbox series

Patch

diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
index 319312770eea..929f9b3ca4f9 100644
--- a/drivers/media/platform/ti-vpe/cal.c
+++ b/drivers/media/platform/ti-vpe/cal.c
@@ -824,20 +824,21 @@  static void csi2_phy_init(struct cal_ctx *ctx)
 
 static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
 {
-	int i;
+	unsigned long timeout;
 
-	for (i = 0; i < 250; i++) {
+	timeout = jiffies + msecs_to_jiffies(750);
+	while (time_before(jiffies, timeout)) {
 		if (reg_read_field(ctx->dev,
 				   CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
 				   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
 		    CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
 			break;
-		usleep_range(1000, 1100);
+		usleep_range(500, 5000);
 	}
-	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n",
+
+	ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done\n",
 		ctx->csi2_port,
-		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i,
-		(i >= 250) ? "(timeout)" : "");
+		reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
 
 	if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
 			   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=