From patchwork Mon Jul 12 08:55:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75703 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rrp-003p8P-Ji; Mon, 12 Jul 2021 09:04:45 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350965AbhGLJH0 (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:26 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45270 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357150AbhGLI60 (ORCPT ); Mon, 12 Jul 2021 04:58:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626080136; x=1628672136; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BkdkwmiGogTIJ3tL5zily69sBf7WMKTObrHPm+hw5mQ=; b=ihMgNSLG9jEAz57qEto6IGNq2y1zKIKRJuvZ01CacfQ0F+lEGzJnlmj/pIggivs8 Pq9aFjOsLjsXGj5Mr5FGWcgrBWS+jPZ2NOLYvQmaMPep2sHrFU4VwCE59acraOei LcLlKW/cAYHHYQ7QxNd8PQ3+he5qAbYs10wtaOVpnro=; X-AuditID: c39127d2-1d8f870000001daf-1b-60ec03881221 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 7A.8D.07599.8830CE06; Mon, 12 Jul 2021 10:55:36 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071210553595-1131631 ; Mon, 12 Jul 2021 10:55:35 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Enrico Scholz , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/6] media: mt9p031: Read back the real clock rate Date: Mon, 12 Jul 2021 10:55:30 +0200 Message-Id: <20210712085535.11907-2-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCLMWRmVeSWpSXmKPExsWyRoCBS7eD+U2CweHZYhbzj5xjtdh77AKL RefEJewWl3fNYbPo2bCV1WLZpj9MFq17j7BbfNryjcmBw2N2x0xWj02rOtk85p0M9Fix8j+T x+dNcgGsUVw2Kak5mWWpRfp2CVwZk5o+sxcc4q/4OfE6UwNjB28XIyeHhICJxOX3p9i7GLk4 hAS2MUrsnfaQCcK5zigxuWUxG0gVm4CRxIJpjWAJEYE2RokdR5rBHGaBp4wSD249ZAepEhZw leh4M40FxGYRUJXYfuw4I4jNK2AjMfnZakaIffISMy99B6rn4OAUsJXY88MSJCwEVHJ9/gYW iHJBiZMzn7BAlF9hlLhxMRzCFpI4vfgsM4jNLKAtsWzha+YJjAKzkLTMQpJawMi0ilEoNzM5 O7UoM1uvIKOyJDVZLyV1EyMwpA9PVL+0g7FvjschRiYOxkOMEhzMSiK833pfJQjxpiRWVqUW 5ccXleakFh9ilOZgURLn3cBbEiYkkJ5YkpqdmlqQWgSTZeLglGpgXOcllqC1ur1g5+HizYdS OWrX//k5ZckZO9aYho/OWon8DdP3cB1YuGv9rjMRiuyvuid8ueBz/vXcO9vuanlsvMvsXjvz +j+N2XH3D9TqrH4Qee1V7l/zvtZzJdrq0/dLxez/rsDZG/hqacnD7fY+VwwKgsofzma8bHnL YCGPtPyss69OZ14XrVNiKc5INNRiLipOBAAr/HxJVwIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Enrico Scholz The real and requested clock can differ and because it is used to calculate PLL values, the real clock rate should be read. Signed-off-by: Enrico Scholz Signed-off-by: Stefan Riedmueller Reviewed-by: Laurent Pinchart --- drivers/media/i2c/mt9p031.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 6eb88ef99783..9dea7c813852 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -229,6 +229,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + unsigned long ext_freq; int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); @@ -239,13 +240,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ext_freq = clk_get_rate(mt9p031->clk); + /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. */ - if (pdata->ext_freq > limits.ext_clock_max) { + if (ext_freq > limits.ext_clock_max) { unsigned int div; - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); div = roundup_pow_of_two(div) / 2; mt9p031->clk_div = min_t(unsigned int, div, 64); @@ -254,7 +257,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } - mt9p031->pll.ext_clock = pdata->ext_freq; + mt9p031->pll.ext_clock = ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true; From patchwork Mon Jul 12 08:55:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75704 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rrs-003p8P-Oi; Mon, 12 Jul 2021 09:04:49 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351143AbhGLJH2 (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:28 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45266 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382027AbhGLJAY (ORCPT ); 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Mon, 12 Jul 2021 10:55:36 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Christian Hemp , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/6] media: mt9p031: Make pixel clock polarity configurable by DT Date: Mon, 12 Jul 2021 10:55:31 +0200 Message-Id: <20210712085535.11907-3-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBLMWRmVeSWpSXmKPExsWyRoCBS7eD+U2CwZvjkhbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZczrnsxUsEmqYv6tP8wNjOvEuhg5OSQETCQaNt1m72Lk4hAS2MYo8ePXLWaQ hJDAdUaJlfutQGw2ASOJBdMamUCKRATaGCV2HGlmAkkwgxRt+AHWICwQIvF0z1F2EJtFQFVi 1p7LYDavgI3EzktPmCC2yUvMvPQdKM7BwSlgK7HnhyXELhuJ6/M3sECUC0qcnPmEBaL8CqPE jYvhELaQxOnFZ5kh1mpLLFv4mnkCo8AsJC2zkKQWMDKtYhTKzUzOTi3KzNYryKgsSU3WS0nd xAgM3cMT1S/tYOyb43GIkYmD8RCjBAezkgjvt95XCUK8KYmVValF+fFFpTmpxYcYpTlYlMR5 N/CWhAkJpCeWpGanphakFsFkmTg4pRoYjXM3CnxLnrImKyv/yUKXbPMvFaYXS+8lBOg+X/HY 9enHJ8cTXe590c1atGrnv0bl3ykaXjFXj1dMW/VANyr43juf/10fxP6/n/mLb9KdS8KbX2Qc mM5wNLNG8GL7+bTZy1ynX/ecea67+Xkun1zm+5mqlz+p3tr38X/wyYmSkgHTJ1m+nJ/qYqrE UpyRaKjFXFScCACFJaeNSwIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Christian Hemp Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9p031.c | 20 +++++++++++++++++++- include/media/i2c/mt9p031.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 588f8eb95984..1f9e98be8066 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1187,6 +1187,7 @@ config VIDEO_MT9P031 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the Aptina (Micron) mt9p031 5 Mpixel camera. diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 9dea7c813852..ea90aff576ba 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aptina-pll.h" @@ -372,6 +373,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) return ret; } + /* Configure the pixel clock polarity */ + if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + return v4l2_ctrl_handler_setup(&mt9p031->ctrls); } @@ -1014,8 +1023,11 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { static struct mt9p031_platform_data * mt9p031_get_pdata(struct i2c_client *client) { - struct mt9p031_platform_data *pdata; + struct mt9p031_platform_data *pdata = NULL; struct device_node *np; + struct v4l2_fwnode_endpoint endpoint = { + .bus_type = V4L2_MBUS_PARALLEL + }; if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) return client->dev.platform_data; @@ -1024,6 +1036,9 @@ mt9p031_get_pdata(struct i2c_client *client) if (!np) return NULL; + if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) + goto done; + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) goto done; @@ -1031,6 +1046,9 @@ mt9p031_get_pdata(struct i2c_client *client) of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); + pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + done: of_node_put(np); return pdata; diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h index 7c29c53aa988..f933cd0be8e5 100644 --- a/include/media/i2c/mt9p031.h +++ b/include/media/i2c/mt9p031.h @@ -10,6 +10,7 @@ struct v4l2_subdev; * @target_freq: Pixel clock frequency */ struct mt9p031_platform_data { + unsigned int pixclk_pol:1; int ext_freq; int target_freq; }; From patchwork Mon Jul 12 08:55:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75705 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rrv-003p8P-G4; Mon, 12 Jul 2021 09:04:51 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351289AbhGLJH3 (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:29 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45266 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382701AbhGLJCC (ORCPT ); Mon, 12 Jul 2021 05:02:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626080136; x=1628672136; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=wRClOOTpYIKz17YoQZPGEsQWo4OJcSdhhZ7l/4lJrYw=; b=BgccaId6E5w9yWtDbWYQLIyC+d5R7YJFmCAp28lx9/XTm/+UFcQwCVOjIE+4nP3h VBNOlz3jDr6M7agWCAaLLONhZURMRpxFhVol1FzXClQLsn6cE9n8cVxN/oPG3ptK LcWaJLsQFubsKNpDuyfGo9rr33c3LKoTtwF1+Hs5Xk0=; X-AuditID: c39127d2-1d8f870000001daf-20-60ec03881f0d Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id EB.8D.07599.8830CE06; Mon, 12 Jul 2021 10:55:36 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071210553628-1131633 ; Mon, 12 Jul 2021 10:55:36 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Dirk Bender , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/6] media: mt9p031: Fix corrupted frame after restarting stream Date: Mon, 12 Jul 2021 10:55:32 +0200 Message-Id: <20210712085535.11907-4-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJLMWRmVeSWpSXmKPExsWyRoCBS7eD+U2CwY/HOhbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZfyafoWt4JpIxeEfNg2MnwW6GDk5JARMJNb0LmPtYuTiEBLYxijRdO8WM4Rz nVHi6YpJzCBVbAJGEgumNTKBJEQE2hgldhxpBnOYBa4xSnz/+4AdpEpYIFhiz/0tTCA2i4Cq xMSHR1hBbF4BG4l9e7+zQuyTl5h56TtQPQcHp4CtxJ4fliBhIaCS6/M3sECUC0qcnPmEBaL8 CqPEjYvhELaQxOnFZ8EOYhbQlli28DXzBEaBWUhaZiFJLWBkWsUolJuZnJ1alJmtV5BRWZKa rJeSuokRGLyHJ6pf2sHYN8fjECMTB+MhRgkOZiUR3m+9rxKEeFMSK6tSi/Lji0pzUosPMUpz sCiJ827gLQkTEkhPLEnNTk0tSC2CyTJxcEo1MGY/En6z9d/ti9M+5TL5Llibyvxa8EyPrfpn HqFjBwznxparv5Xkk2K8eFJYr2lx176b/ZM9ji/xPZu3Z1bki2vzdTJZ/wYxsaQd+hcruf9K v/ruzAmL+mem+h2a88Z9ru60NEu2W1wy+60tG/b5HFi2ULzGMfy8FNMqdsnLv/m9ixh3lIT9 vabEUpyRaKjFXFScCACOmuZoTAIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Dirk Bender To prevent corrupted frames after starting and stopping the sensor its datasheet specifies a specific pause sequence to follow: Stopping: Set Pause_Restart Bit -> Set Restart Bit -> Set Chip_Enable Off Restarting: Set Chip_Enable On -> Clear Pause_Restart Bit The Restart Bit is cleared automatically and must not be cleared manually as this would cause undefined behavior. Signed-off-by: Dirk Bender Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ea90aff576ba..ee2777059682 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -79,7 +79,9 @@ #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) -#define MT9P031_FRAME_RESTART 0x0b +#define MT9P031_RESTART 0x0b +#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) +#define MT9P031_FRAME_RESTART (1 << 0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d #define MT9P031_RST_ENABLE 1 @@ -456,9 +458,23 @@ static int mt9p031_set_params(struct mt9p031 *mt9p031) static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) { struct mt9p031 *mt9p031 = to_mt9p031(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + int val; int ret; if (!enable) { + /* enable pause restart */ + val = MT9P031_FRAME_PAUSE_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + + /* enable restart + keep pause restart set */ + val |= MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + /* Stop sensor readout */ ret = mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); @@ -478,6 +494,16 @@ static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) if (ret < 0) return ret; + /* + * - clear pause restart + * - don't clear restart as clearing restart manually can cause + * undefined behavior + */ + val = MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + return mt9p031_pll_enable(mt9p031); } From patchwork Mon Jul 12 08:55:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75706 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rs2-003p9g-4Q; Mon, 12 Jul 2021 09:04:58 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356419AbhGLJHc (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:32 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45250 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382703AbhGLJCC (ORCPT ); Mon, 12 Jul 2021 05:02:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626080136; x=1628672136; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=qN6QTxTTKZhnbCx2gpq04CN4bCn0nWKxKQ/ztel5F0Q=; b=tnzn6gSIwQIIhH9QahxepfGUtKvtHYlQtPCVyqfYIsKPyTDJXx9lGZD+Qatehl/g mQ//wp0YHOknpVUUapcbrCggkAQJ40rxHdN2YdIVX+zHPG6AZ2wChr6962T0nSaf qLnpZcXnXsp6OZsGdAQZgK0GL8j1k/L0k3b0/CewwHo=; X-AuditID: c39127d2-1e4f970000001daf-23-60ec0388a964 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id AC.8D.07599.8830CE06; Mon, 12 Jul 2021 10:55:36 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071210553654-1131634 ; Mon, 12 Jul 2021 10:55:36 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/6] media: mt9p031: Use BIT macro Date: Mon, 12 Jul 2021 10:55:33 +0200 Message-Id: <20210712085535.11907-5-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:36 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFLMWRmVeSWpSXmKPExsWyRoCBS7eD+U2Cwan9phbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZRx5uZqtYKdsxdqHR9gaGJ9IdDFyckgImEgc/bqGpYuRi0NIYBujxObDj6Gc 64wSW6a1sIFUsQkYSSyY1sgEkhARaGOU2HGkGcxhFtjCKDH98nKwKmEBU4lXz1eA2SwCqhI7 d59gB7F5BWwk3nzaxQ6xT15i5qXvQDYHB6eArcSeH5YgYSGgkuvzN7BAlAtKnJz5hAWi/Aqj xI2L4RC2kMTpxWeZQWxmAW2JZQtfM09gFJiFpGUWktQCRqZVjEK5mcnZqUWZ2XoFGZUlqcl6 KambGIHhe3ii+qUdjH1zPA4xMnEwHmKU4GBWEuH91vsqQYg3JbGyKrUoP76oNCe1+BCjNAeL kjjvBt6SMCGB9MSS1OzU1ILUIpgsEwenVAOjYspzOcWIhNveU0o4jv+aJNLIP1d+/zUF4ctt /7jubuWdwFt12knQ00fKYr3egoLycwmLuvhNf6Yc5u+cIJB1KI1p78wVbadN2L++feVb2f3m XS3jn3tzczyqT4nJ9y7kWL39jdoMtTXTJqxoq39eGZ5kNf32+nff/ji+SnB+doIzuftYu32Y EktxRqKhFnNRcSIArGzA3E0CAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Make use of the BIT macro for setting individual bits. This improves readability and safety with respect to shifts. When on it also remove two zero value disable defines. Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ee2777059682..cbce8b88dbcf 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -76,40 +76,38 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a -#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_INVERT BIT(15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_RESTART 0x0b -#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) -#define MT9P031_FRAME_RESTART (1 << 0) +#define MT9P031_FRAME_PAUSE_RESTART BIT(1) +#define MT9P031_FRAME_RESTART BIT(0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d -#define MT9P031_RST_ENABLE 1 -#define MT9P031_RST_DISABLE 0 +#define MT9P031_RST_ENABLE BIT(0) #define MT9P031_READ_MODE_1 0x1e #define MT9P031_READ_MODE_2 0x20 -#define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) -#define MT9P031_READ_MODE_2_COL_MIR (1 << 14) -#define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) +#define MT9P031_READ_MODE_2_ROW_MIR BIT(15) +#define MT9P031_READ_MODE_2_COL_MIR BIT(14) +#define MT9P031_READ_MODE_2_ROW_BLC BIT(6) #define MT9P031_ROW_ADDRESS_MODE 0x22 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 #define MT9P031_GLOBAL_GAIN 0x35 #define MT9P031_GLOBAL_GAIN_MIN 8 #define MT9P031_GLOBAL_GAIN_MAX 1024 #define MT9P031_GLOBAL_GAIN_DEF 8 -#define MT9P031_GLOBAL_GAIN_MULT (1 << 6) +#define MT9P031_GLOBAL_GAIN_MULT BIT(6) #define MT9P031_ROW_BLACK_TARGET 0x49 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b #define MT9P031_GREEN1_OFFSET 0x60 #define MT9P031_GREEN2_OFFSET 0x61 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 -#define MT9P031_BLC_MANUAL_BLC (1 << 0) +#define MT9P031_BLC_MANUAL_BLC BIT(0) #define MT9P031_RED_OFFSET 0x63 #define MT9P031_BLUE_OFFSET 0x64 #define MT9P031_TEST_PATTERN 0xa0 #define MT9P031_TEST_PATTERN_SHIFT 3 -#define MT9P031_TEST_PATTERN_ENABLE (1 << 0) -#define MT9P031_TEST_PATTERN_DISABLE (0 << 0) +#define MT9P031_TEST_PATTERN_ENABLE BIT(0) #define MT9P031_TEST_PATTERN_GREEN 0xa1 #define MT9P031_TEST_PATTERN_RED 0xa2 #define MT9P031_TEST_PATTERN_BLUE 0xa3 @@ -199,7 +197,7 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); if (ret < 0) return ret; - ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); + ret = mt9p031_write(client, MT9P031_RST, 0); if (ret < 0) return ret; @@ -794,8 +792,7 @@ static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) if (ret < 0) return ret; - return mt9p031_write(client, MT9P031_TEST_PATTERN, - MT9P031_TEST_PATTERN_DISABLE); + return mt9p031_write(client, MT9P031_TEST_PATTERN, 0); } ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); From patchwork Mon Jul 12 08:55:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75707 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rs3-003p9g-Bf; Mon, 12 Jul 2021 09:04:59 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357684AbhGLJHl (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:41 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45266 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382895AbhGLJC3 (ORCPT ); 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Mon, 12 Jul 2021 10:55:36 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/6] media: dt-bindings: mt9p031: Convert bindings to yaml Date: Mon, 12 Jul 2021 10:55:34 +0200 Message-Id: <20210712085535.11907-6-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:37, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:37 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFLMWRmVeSWpSXmKPExsWyRoCBS7eT+U2CwYxznBbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZRybv5294KlKxdPdl5kaGO/LdDFycEgImEh0XjTvYuTiEBLYxiix9+ZxJgjn OqPEspUvGLsYOTnYBIwkFkxrBEuICLQxSuw40gzmMAtsYZSYfnk5G0iVsICvxJXDD9lBbBYB VYkFvS+ZQGxeARuJDx3NYLaEgLzEzEvf2UFWcwrYSuz5YQkSFgIquT5/AwtEuaDEyZlPWEDm SwhcAZr/8DYzRK+QxOnFZ8FsZgFtiWULXzNPYBSYhaRnFpLUAkamVYxCuZnJ2alFmdl6BRmV JanJeimpmxiB4Xt4ovqlHYx9czwOMTJxMB5ilOBgVhLh/db7KkGINyWxsiq1KD++qDQntfgQ ozQHi5I47wbekjAhgfTEktTs1NSC1CKYLBMHp1QDY893mcln1/2a+fbd2o9nfSZ9uVVWtmDb 8Q+7dzGk3XftnK0XzMS1Y0tHcMujK9Ob+fayrVQyj3E8+a+O9ffrPWu3nmhfs9XwZMjjn2q8 zGE3Aw9MLY3Tt37I4Rsxh13hjC3XT9O7z0S9eH7MeBbzM/pKvdOK9XIJF3jer19yU2xBduSW I3f/KKcrsRRnJBpqMRcVJwIA551A3E0CAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Convert mt9p031 sensor bindings to yaml schema. Also update the MAINTAINERS entry. Although input-clock-frequency and pixel-clock-frequency have not been definded as endpoint propierties in the textual bindings, the sensor does parse them from the endpoint. Thus move these properties to the endpoint in the new yaml bindings. Signed-off-by: Stefan Riedmueller --- .../bindings/media/i2c/aptina,mt9p031.yaml | 75 +++++++++++++++++++ .../devicetree/bindings/media/i2c/mt9p031.txt | 40 ---------- MAINTAINERS | 1 + 3 files changed, 76 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml delete mode 100644 Documentation/devicetree/bindings/media/i2c/mt9p031.txt diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml new file mode 100644 index 000000000000..ad9a2db73d86 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/aptina,mt9p031.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor + +maintainers: + - Laurent Pinchart + +description: | + The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor + with an active array size of 2592H x 1944V. It is programmable through a + simple two-wire serial interface. + +properties: + compatible: + enum: + - aptina,mt9p031 + - aptina,mt9p031m + + reg: + description: I2C device address + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: Chip reset GPIO + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + input-clock-frequency: true + pixel-clock-frequency: true + + required: + - input-clock-frequency + - pixel-clock-frequency + +required: + - compatible + - reg + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt9p031@5d { + compatible = "aptina,mt9p031"; + reg = <0x5d>; + reset-gpios = <&gpio_sensor 0 0>; + + port { + mt9p031_1: endpoint { + input-clock-frequency = <6000000>; + pixel-clock-frequency = <96000000>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt b/Documentation/devicetree/bindings/media/i2c/mt9p031.txt deleted file mode 100644 index cb60443ff78f..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor - -The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a simple -two-wire serial interface. - -Required Properties: -- compatible: value should be either one among the following - (a) "aptina,mt9p031" for mt9p031 sensor - (b) "aptina,mt9p031m" for mt9p031m sensor - -- input-clock-frequency: Input clock frequency. - -- pixel-clock-frequency: Pixel clock frequency. - -Optional Properties: -- reset-gpios: Chip reset GPIO - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - mt9p031@5d { - compatible = "aptina,mt9p031"; - reg = <0x5d>; - reset-gpios = <&gpio3 30 0>; - - port { - mt9p031_1: endpoint { - input-clock-frequency = <6000000>; - pixel-clock-frequency = <96000000>; - }; - }; - }; - ... - }; diff --git a/MAINTAINERS b/MAINTAINERS index a61f4f3b78a9..33dd81237a91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12635,6 +12635,7 @@ M: Laurent Pinchart L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml F: drivers/media/i2c/mt9p031.c F: include/media/i2c/mt9p031.h From patchwork Mon Jul 12 08:55:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75708 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rs4-003p9g-Gq; Mon, 12 Jul 2021 09:05:00 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357707AbhGLJHn (ORCPT + 1 other); Mon, 12 Jul 2021 05:07:43 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:45270 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382904AbhGLJCa (ORCPT ); Mon, 12 Jul 2021 05:02:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626080137; x=1628672137; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=uC8cBQL1xFdGBkFPFEx8KFNhS1ChOLH8o8ZHun1kY00=; b=bH8rxWtzV2H/DIIZ3MBOQc2kPIm60IM50J0Bm2EbE2gWRXG4XkmRsq5PJwlYohek +n5es4yCod/CMyBGpPdAnfGIbkl56xI3ST6Z+Vc5VgGYD7rK2FxsjwIDQC6COx+J MfT22lu6dLtwpalX/Ecz4qMbA5eOs1F3h340DUcZKOM=; X-AuditID: c39127d2-1e4f970000001daf-27-60ec03896928 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id ED.8D.07599.9830CE06; Mon, 12 Jul 2021 10:55:37 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071210553709-1131636 ; Mon, 12 Jul 2021 10:55:37 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/6] media: dt-bindings: mt9p031: Add missing required properties Date: Mon, 12 Jul 2021 10:55:35 +0200 Message-Id: <20210712085535.11907-7-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712085535.11907-1-s.riedmueller@phytec.de> References: <20210712085535.11907-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:37, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 12.07.2021 10:55:37 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWyRoCBS7eT+U2CwZ2r0hbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZew8No2toI+3Yu+EgywNjB84uxg5OSQETCRef/7I1MXIxSEksI1RYur2HawQ znVGibVLtjKBVLEJGEksmNYIViUi0MYoseNIM5jDLLCFUWL65eVsIFXCAiESc5eeYgGxWQRU JV4vXcUMYvMK2EjsujmNBWKfvMTMS9/Zuxg5ODgFbCX2/LAECQsBlVyfv4EFolxQ4uTMJywg 8yUErgDNf3ibGaJXSOL04rNgNrOAtsSyha+ZJzAKzELSMwtJagEj0ypGodzM5OzUosxsvYKM ypLUZL2U1E2MwAA+PFH90g7GvjkehxiZOBgPMUpwMCuJ8H7rfZUgxJuSWFmVWpQfX1Sak1p8 iFGag0VJnHcDb0mYkEB6YklqdmpqQWoRTJaJg1OqgTF43mvZc8sVlpQkeuwtfvDrxHub9RGv Fp+d3PM24hrzx/55zIbzipc+nuy/yGfeScts58SUDQHJZfvjImWvya/YvJPH+amh0GqliL6f T4z5eXKKD6/TmTZpncsn14aHno6b+mKvJZrd1jVWddNZ9v6UW8qCa56zOQxSpcpfWTgUBE/P tUiwjVRiKc5INNRiLipOBAAeoPmeTgIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Add missing required clocks and supply regulator properties for the sensor input clock and vdd, vdd_io and vaa supply regulators. Signed-off-by: Stefan Riedmueller Reviewed-by: Rob Herring --- .../bindings/media/i2c/aptina,mt9p031.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml index ad9a2db73d86..487a3facfcbc 100644 --- a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml @@ -24,6 +24,18 @@ properties: description: I2C device address maxItems: 1 + clocks: + maxItems: 1 + + vdd-supply: + description: Digital supply voltage, 1.8 V + + vdd_io-supply: + description: I/O supply voltage, 1.8 or 2.8 V + + vaa-supply: + description: Analog supply voltage, 2.8 V + reset-gpios: maxItems: 1 description: Chip reset GPIO @@ -48,6 +60,10 @@ properties: required: - compatible - reg + - clocks + - vdd-supply + - vdd_io-supply + - vaa-supply - port additionalProperties: false @@ -63,6 +79,12 @@ examples: reg = <0x5d>; reset-gpios = <&gpio_sensor 0 0>; + clocks = <&sensor_clk>; + + vdd-supply = <®_vdd>; + vdd_io-supply = <®_vdd_io>; + vaa-supply = <®_vaa>; + port { mt9p031_1: endpoint { input-clock-frequency = <6000000>;