From patchwork Thu Jul 8 09:19:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75626 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QBz-00Fu7s-2v; Thu, 08 Jul 2021 09:19:35 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbhGHJWN (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:13 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46322 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231336AbhGHJWG (ORCPT ); Thu, 8 Jul 2021 05:22:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1625735962; x=1628327962; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BkdkwmiGogTIJ3tL5zily69sBf7WMKTObrHPm+hw5mQ=; b=rsDn7W+Eolv4Mz0drg9zYCDSK7HUlrrO+iTCKHckYaIkNoYOg5rdfnT3eo95CWok Y6eUtyWJgMIVVUS8J5g+nXoZebtGzYzz1Rylc9REWvkJCqATm4h4Br3+fkqs427W 9vOMls1dPyzVEciW6dherIOt4MOpfxzqkMdGbs0O1a4=; X-AuditID: c39127d2-1d8f870000001daf-7d-60e6c31a43c9 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 37.B7.07599.A13C6E06; Thu, 8 Jul 2021 11:19:22 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021070811192218-1113441 ; Thu, 8 Jul 2021 11:19:22 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Enrico Scholz , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/6] media: mt9p031: Read back the real clock rate Date: Thu, 8 Jul 2021 11:19:17 +0200 Message-Id: <20210708091922.5508-2-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:22, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:22 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsWyRoCBS1fq8LMEg56HShbzj5xjtdh77AKL RefEJewWl3fNYbPo2bCV1WLZpj9MFq17j7BbfNryjcmBw2N2x0xWj02rOtk85p0M9Fix8j+T x+dNcgGsUVw2Kak5mWWpRfp2CVwZk5o+sxcc4q/4OfE6UwNjB28XIyeHhICJxPm7N1i7GLk4 hAS2MUr83LecCcK5xiixcOU+VpAqNgEjiQXTGsESIgJtjBI7jjSDOcwCTxklHtx6yA5SJSzg KvHl/VmwDhYBFYnjh5axgNi8AtYSc6ZcYoLYJy8x89J3oHoODk4BG4mu/hSQsBBQybFZt1gh ygUlTs58wgIyX0LgCqNE/8dmdoheIYnTi88yg9jMAtoSyxa+Zp7AKDALSc8sJKkFjEyrGIVy M5OzU4sys/UKMipLUpP1UlI3MQKD+vBE9Us7GPvmeBxiZOJgPMQowcGsJMJrNONZghBvSmJl VWpRfnxRaU5q8SFGaQ4WJXHeDbwlYUIC6YklqdmpqQWpRTBZJg5OqQbG8OJzb1ZnRTEd2iwW W3cpNJNvzXLPpU8X7vzwuVJ5Tu12xnn22QrCsY/WLvtkVlO+h2XVhJsnJy/8xRuy+GPolHv5 Dk61V4Q9DtfaXQmOkHlVMLfT3bZrh9qb/0e0ZgkfceOUOLUny2gbO69f6X3XjgvS/y8vLp6m tHHj17231wrPuzC7NdVKQomlOCPRUIu5qDgRANAzIPpYAgAA Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Enrico Scholz The real and requested clock can differ and because it is used to calculate PLL values, the real clock rate should be read. Signed-off-by: Enrico Scholz Signed-off-by: Stefan Riedmueller Reviewed-by: Laurent Pinchart --- drivers/media/i2c/mt9p031.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 6eb88ef99783..9dea7c813852 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -229,6 +229,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + unsigned long ext_freq; int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); @@ -239,13 +240,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ext_freq = clk_get_rate(mt9p031->clk); + /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. */ - if (pdata->ext_freq > limits.ext_clock_max) { + if (ext_freq > limits.ext_clock_max) { unsigned int div; - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); div = roundup_pow_of_two(div) / 2; mt9p031->clk_div = min_t(unsigned int, div, 64); @@ -254,7 +257,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } - mt9p031->pll.ext_clock = pdata->ext_freq; + mt9p031->pll.ext_clock = ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true; From patchwork Thu Jul 8 09:19:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75625 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QBx-00Fu7s-Rq; Thu, 08 Jul 2021 09:19:34 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231402AbhGHJWM (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:12 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46340 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231356AbhGHJWG (ORCPT ); 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Thu, 8 Jul 2021 11:19:22 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Christian Hemp , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] media: mt9p031: Make pixel clock polarity configurable by DT Date: Thu, 8 Jul 2021 11:19:18 +0200 Message-Id: <20210708091922.5508-3-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:22, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:22 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJLMWRmVeSWpSXmKPExsWyRoCBS1fq8LMEg+nbTCzmHznHatE5cQm7 xeVdc9gsejZsZbVYtukPk0Xr3iPsFp+2fGNyYPeY3TGT1WPTqk42j3knAz0+b5ILYInisklJ zcksSy3St0vgypjXPZmpYJNUxfxbf5gbGNeJdTFyckgImEg8mXOcsYuRi0NIYBujxNOrz1kg nGuMErtnLWUGqWITMJJYMK2RCSQhItDGKLHjSDMTSIJZ4DqjxIYfQEUcHMICIRKzb7KChFkE VCTeTr8CVsIrYC2x9fdXJoht8hIzL31nBynnFLCR6OpPAQkLAZUcm3WLFaJcUOLkzCdgN0gI XGGU6P/YzA7RKyRxevFZZoi12hLLFr5mnsAoMAtJzywkqQWMTKsYhXIzk7NTizKz9QoyKktS k/VSUjcxAoP38ET1SzsY++Z4HGJk4mA8xCjBwawkwms041mCEG9KYmVValF+fFFpTmrxIUZp DhYlcd4NvCVhQgLpiSWp2ampBalFMFkmDk6pBsbY9/eVV/oXKQkmZ09Xv5vF9yLO/JTHdc7E Gy/V7//eG8u34GxTw9sDmf09yY/evm02jXz7r8nbZsoRw+niNSVvl9/UnZ9ybpXWvR31z/hC PgjNO7jl7eck5ZJ3TnM9W9+WH9xwLLj+3nHd/yqz9/blWNr0nTgS9PuRJFdt5M+SxTdnWi46 4TRLiaU4I9FQi7moOBEAFmghakwCAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Christian Hemp Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9p031.c | 20 +++++++++++++++++++- include/media/i2c/mt9p031.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 588f8eb95984..1f9e98be8066 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1187,6 +1187,7 @@ config VIDEO_MT9P031 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the Aptina (Micron) mt9p031 5 Mpixel camera. diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 9dea7c813852..ea90aff576ba 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aptina-pll.h" @@ -372,6 +373,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) return ret; } + /* Configure the pixel clock polarity */ + if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + return v4l2_ctrl_handler_setup(&mt9p031->ctrls); } @@ -1014,8 +1023,11 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { static struct mt9p031_platform_data * mt9p031_get_pdata(struct i2c_client *client) { - struct mt9p031_platform_data *pdata; + struct mt9p031_platform_data *pdata = NULL; struct device_node *np; + struct v4l2_fwnode_endpoint endpoint = { + .bus_type = V4L2_MBUS_PARALLEL + }; if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) return client->dev.platform_data; @@ -1024,6 +1036,9 @@ mt9p031_get_pdata(struct i2c_client *client) if (!np) return NULL; + if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) + goto done; + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) goto done; @@ -1031,6 +1046,9 @@ mt9p031_get_pdata(struct i2c_client *client) of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); + pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + done: of_node_put(np); return pdata; diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h index 7c29c53aa988..f933cd0be8e5 100644 --- a/include/media/i2c/mt9p031.h +++ b/include/media/i2c/mt9p031.h @@ -10,6 +10,7 @@ struct v4l2_subdev; * @target_freq: Pixel clock frequency */ struct mt9p031_platform_data { + unsigned int pixclk_pol:1; int ext_freq; int target_freq; }; From patchwork Thu Jul 8 09:19:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75627 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QC0-00Fu7s-4A; Thu, 08 Jul 2021 09:19:36 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231392AbhGHJWO (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:14 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46340 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231364AbhGHJWI (ORCPT ); Thu, 8 Jul 2021 05:22:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1625735963; x=1628327963; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=wRClOOTpYIKz17YoQZPGEsQWo4OJcSdhhZ7l/4lJrYw=; b=KW0w3+ZRY0fiqTjIKRcRVqxLA96AzRLeCgkZQjvan7tY8iu5QEsV07+SGohYoSjJ UaSyfmEtYChmmt4vpM3Lxh+MJLI2hDxkXEFDPBwH8MzD1hr31griEZU50Wo103Yt zZY50COSGW5ph9Xzr5V1lQDuCkQtpcBxpIX//n0exHQ=; X-AuditID: c39127d2-1e4f970000001daf-82-60e6c31b1b30 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id A8.B7.07599.B13C6E06; Thu, 8 Jul 2021 11:19:23 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021070811192274-1113443 ; Thu, 8 Jul 2021 11:19:22 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Dirk Bender , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/6] media: mt9p031: Fix corrupted frame after restarting stream Date: Thu, 8 Jul 2021 11:19:19 +0200 Message-Id: <20210708091922.5508-4-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:22, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBLMWRmVeSWpSXmKPExsWyRoCBS1f68LMEg66dPBbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZfyafoWt4JpIxeEfNg2MnwW6GDk5JARMJL7+W80MYgsJbGOUmHievYuRC8i+ xijxZGsTI0iCTcBIYsG0RiaQhIhAG6PEjiPNYA4zSNX3vw/YQaqEBYIl1jf3sIHYLAIqEruu 72TpYuTg4BWwltj7hBdim7zEzEvf2UHCnAI2El39KRCLrSWOzbrFCmLzCghKnJz5hAVkvITA FaAjvh1lg+gVkji9+CzYpcwC2hLLFr5mnsAoMAtJzywkqQWMTKsYhXIzk7NTizKz9QoyKktS k/VSUjcxAkP38ET1SzsY++Z4HGJk4mA8xCjBwawkwms041mCEG9KYmVValF+fFFpTmrxIUZp DhYlcd4NvCVhQgLpiSWp2ampBalFMFkmDk6pBkZp7s27rdrN4iUc/my7nZCzQvzqgapXN6QW 771Y/2mpbsDMC+GfLTI9Xi88uah618VVrYG8Z8tmJ5hl1vIv8qrqLex7uHgF07Fp5cXW32YI bEj6d/4w69Rdk+NFrHaUTrP4PPXOlL0iHeecAzO+n9OaF2X/piZS6skpz80KG753rtgZeVhz r/VFJZbijERDLeai4kQAUelCpEsCAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no From: Dirk Bender To prevent corrupted frames after starting and stopping the sensor its datasheet specifies a specific pause sequence to follow: Stopping: Set Pause_Restart Bit -> Set Restart Bit -> Set Chip_Enable Off Restarting: Set Chip_Enable On -> Clear Pause_Restart Bit The Restart Bit is cleared automatically and must not be cleared manually as this would cause undefined behavior. Signed-off-by: Dirk Bender Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ea90aff576ba..ee2777059682 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -79,7 +79,9 @@ #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) -#define MT9P031_FRAME_RESTART 0x0b +#define MT9P031_RESTART 0x0b +#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) +#define MT9P031_FRAME_RESTART (1 << 0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d #define MT9P031_RST_ENABLE 1 @@ -456,9 +458,23 @@ static int mt9p031_set_params(struct mt9p031 *mt9p031) static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) { struct mt9p031 *mt9p031 = to_mt9p031(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + int val; int ret; if (!enable) { + /* enable pause restart */ + val = MT9P031_FRAME_PAUSE_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + + /* enable restart + keep pause restart set */ + val |= MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + /* Stop sensor readout */ ret = mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); @@ -478,6 +494,16 @@ static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) if (ret < 0) return ret; + /* + * - clear pause restart + * - don't clear restart as clearing restart manually can cause + * undefined behavior + */ + val = MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + return mt9p031_pll_enable(mt9p031); } From patchwork Thu Jul 8 09:19:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75628 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QC1-00Fu7s-8E; Thu, 08 Jul 2021 09:19:37 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231293AbhGHJWP (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:15 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46318 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231367AbhGHJWI (ORCPT ); Thu, 8 Jul 2021 05:22:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1625735963; x=1628327963; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=qN6QTxTTKZhnbCx2gpq04CN4bCn0nWKxKQ/ztel5F0Q=; b=A4i+7U66/EeJ0fXtuAhMbmw2t36WkZcfmKKZLIwKOkwXXmmT2hKQdJyVx+hoo0A9 GtxOI3VgpFA/lIlre1MEByF6d/jQJh/hPxCWiM9nyiyXoQinwEv6PnAeEQqZObpQ cpm/7O6n/z5xMx+5GS6y1XeWF7Cy+jMnN8UyIiA5HCw=; X-AuditID: c39127d2-1e4f970000001daf-86-60e6c31b0742 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 69.B7.07599.B13C6E06; Thu, 8 Jul 2021 11:19:23 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021070811192301-1113444 ; Thu, 8 Jul 2021 11:19:23 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/6] media: mt9p031: Use BIT macro Date: Thu, 8 Jul 2021 11:19:20 +0200 Message-Id: <20210708091922.5508-5-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWyRoCBS1f68LMEg75bEhbzj5xjteicuITd 4vKuOWwWPRu2slos2/SHyaJ17xF2i09bvjE5sHvM7pjJ6rFpVSebx7yTgR6fN8kFsERx2aSk 5mSWpRbp2yVwZRx5uZqtYKdsxdqHR9gaGJ9IdDFyckgImEhcu/mVtYuRi0NIYBujxNOtZ9kg nGuMEu///mECqWITMJJYMK2RCSQhItDGKLHjSDOYwyywhVFi+uXlbCBVwgKmElsmPATrYBFQ kXjbvJkFxOYVsJZYvqWJBWKfvMTMS9/Zuxg5ODgFbCS6+lNAwkJAJcdm3WKFKBeUODnzCQvI fAmBK4wS838tY4PoFZI4vfgsM4jNLKAtsWzha+YJjAKzkPTMQpJawMi0ilEoNzM5O7UoM1uv IKOyJDVZLyV1EyMwgA9PVL+0g7FvjschRiYOxkOMEhzMSiK8RjOeJQjxpiRWVqUW5ccXleak Fh9ilOZgURLn3cBbEiYkkJ5YkpqdmlqQWgSTZeLglGpgzC1aLf5wu70BZ9T5z7pH088V/3r+ WPCXSv+Vk5qv1Ba0rixOEUm5bp/348Kjnzy+V++GfsotZT55anb2/jvfjJ8cS5338t3JuqjL E+T3KSXWb5z2nXdJfLsk9/znISdKX0rOaVsZJd4beaRn/7a1PRvnlxar7/xb9db82OnC+wGH 4qqVn19sXarEUpyRaKjFXFScCAA2aExtTgIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Make use of the BIT macro for setting individual bits. This improves readability and safety with respect to shifts. When on it also remove two zero value disable defines. Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ee2777059682..cbce8b88dbcf 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -76,40 +76,38 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a -#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_INVERT BIT(15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_RESTART 0x0b -#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) -#define MT9P031_FRAME_RESTART (1 << 0) +#define MT9P031_FRAME_PAUSE_RESTART BIT(1) +#define MT9P031_FRAME_RESTART BIT(0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d -#define MT9P031_RST_ENABLE 1 -#define MT9P031_RST_DISABLE 0 +#define MT9P031_RST_ENABLE BIT(0) #define MT9P031_READ_MODE_1 0x1e #define MT9P031_READ_MODE_2 0x20 -#define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) -#define MT9P031_READ_MODE_2_COL_MIR (1 << 14) -#define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) +#define MT9P031_READ_MODE_2_ROW_MIR BIT(15) +#define MT9P031_READ_MODE_2_COL_MIR BIT(14) +#define MT9P031_READ_MODE_2_ROW_BLC BIT(6) #define MT9P031_ROW_ADDRESS_MODE 0x22 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 #define MT9P031_GLOBAL_GAIN 0x35 #define MT9P031_GLOBAL_GAIN_MIN 8 #define MT9P031_GLOBAL_GAIN_MAX 1024 #define MT9P031_GLOBAL_GAIN_DEF 8 -#define MT9P031_GLOBAL_GAIN_MULT (1 << 6) +#define MT9P031_GLOBAL_GAIN_MULT BIT(6) #define MT9P031_ROW_BLACK_TARGET 0x49 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b #define MT9P031_GREEN1_OFFSET 0x60 #define MT9P031_GREEN2_OFFSET 0x61 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 -#define MT9P031_BLC_MANUAL_BLC (1 << 0) +#define MT9P031_BLC_MANUAL_BLC BIT(0) #define MT9P031_RED_OFFSET 0x63 #define MT9P031_BLUE_OFFSET 0x64 #define MT9P031_TEST_PATTERN 0xa0 #define MT9P031_TEST_PATTERN_SHIFT 3 -#define MT9P031_TEST_PATTERN_ENABLE (1 << 0) -#define MT9P031_TEST_PATTERN_DISABLE (0 << 0) +#define MT9P031_TEST_PATTERN_ENABLE BIT(0) #define MT9P031_TEST_PATTERN_GREEN 0xa1 #define MT9P031_TEST_PATTERN_RED 0xa2 #define MT9P031_TEST_PATTERN_BLUE 0xa3 @@ -199,7 +197,7 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); if (ret < 0) return ret; - ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); + ret = mt9p031_write(client, MT9P031_RST, 0); if (ret < 0) return ret; @@ -794,8 +792,7 @@ static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) if (ret < 0) return ret; - return mt9p031_write(client, MT9P031_TEST_PATTERN, - MT9P031_TEST_PATTERN_DISABLE); + return mt9p031_write(client, MT9P031_TEST_PATTERN, 0); } ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); From patchwork Thu Jul 8 09:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75629 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QC2-00Fu7s-DO; Thu, 08 Jul 2021 09:19:38 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231429AbhGHJWQ (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:16 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46322 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231391AbhGHJWJ (ORCPT ); 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Thu, 8 Jul 2021 11:19:23 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/6] media: dt-bindings: mt9p031: Convert bindings to yaml Date: Thu, 8 Jul 2021 11:19:21 +0200 Message-Id: <20210708091922.5508-6-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWyRoCBS1f68LMEg5v7tSzmHznHatE5cQm7 xeVdc9gsejZsZbVYtukPk0Xr3iPsFp+2fGNyYPeY3TGT1WPTqk42j3knAz0+b5ILYInisklJ zcksSy3St0vgyphy+QdzwVOlipfN05kbGDukuxg5OSQETCQe3t/B3MXIxSEksI1R4uXC3WwQ zjVGiU1bPrCBVLEJGEksmNbIBJIQEWhjlNhxpBnMYRbYwigx/fJysCphAV+J83teMYPYLAIq Er++nGQBsXkFrCVW3r3IBLFPXmLmpe/sXYwcHJwCNhJd/SkgYSGgkmOzbrFClAtKnJz5hAVk voTAFUaJ+b+WsUH0CkmcXnwWbD6zgLbEsoWvmScwCsxC0jMLSWoBI9MqRqHczOTs1KLMbL2C jMqS1GS9lNRNjMAAPjxR/dIOxr45HocYmTgYDzFKcDArifAazXiWIMSbklhZlVqUH19UmpNa fIhRmoNFSZx3A29JmJBAemJJanZqakFqEUyWiYNTqoExxpf1KFfFwphPLzVy3NYcbrzaUd29 T8vh6fewtn+3vIorowIWeavXujjaTfnoaOea/Mtg0jumqDeF0pXXVvpHa6f1nfq06IN7V4Xz /s/+/mtFXFapOIpM47n8SH+R/xqN7RJ8EsevL4hQurSWIZK9cOI+PomtN+375yocNDxhkyOh 1X+FQ0OJpTgj0VCLuag4EQD1v87PTgIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Convert mt9p031 sensor bindings to yaml schema. Also update the MAINTAINERS entry. Signed-off-by: Stefan Riedmueller --- .../bindings/media/i2c/aptina,mt9p031.yaml | 75 +++++++++++++++++++ .../devicetree/bindings/media/i2c/mt9p031.txt | 40 ---------- MAINTAINERS | 1 + 3 files changed, 76 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml delete mode 100644 Documentation/devicetree/bindings/media/i2c/mt9p031.txt diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml new file mode 100644 index 000000000000..7de62e339895 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/mt9p031.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor + +maintainers: + - Laurent Pinchart + +description: | + The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor + with an active array size of 2592H x 1944V. It is programmable through a + simple two-wire serial interface. + +properties: + compatible: + enum: + - aptina,mt9p031 + - aptina,mt9p031m + + reg: + description: I2C device address + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: Chip reset GPIO + + port: + $ref: /schemas/graph.yaml#/properties/port + addittionalProeprties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + input-clock-frequency: true + pixel-clock-frequency: true + + required: + - input-clock-frequency + - pixel-clock-frequency + +required: + - compatible + - reg + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt9p031@5d { + compatible = "aptina,mt9p031"; + reg = <0x5d>; + reset-gpios = <&gpio_sensor 0 0>; + + port { + mt9p031_1: endpoint { + input-clock-frequency = <6000000>; + pixel-clock-frequency = <96000000>; + }; + }; + }: + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt b/Documentation/devicetree/bindings/media/i2c/mt9p031.txt deleted file mode 100644 index cb60443ff78f..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor - -The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a simple -two-wire serial interface. - -Required Properties: -- compatible: value should be either one among the following - (a) "aptina,mt9p031" for mt9p031 sensor - (b) "aptina,mt9p031m" for mt9p031m sensor - -- input-clock-frequency: Input clock frequency. - -- pixel-clock-frequency: Pixel clock frequency. - -Optional Properties: -- reset-gpios: Chip reset GPIO - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - mt9p031@5d { - compatible = "aptina,mt9p031"; - reg = <0x5d>; - reset-gpios = <&gpio3 30 0>; - - port { - mt9p031_1: endpoint { - input-clock-frequency = <6000000>; - pixel-clock-frequency = <96000000>; - }; - }; - }; - ... - }; diff --git a/MAINTAINERS b/MAINTAINERS index c7456776ace5..f2123226baae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12610,6 +12610,7 @@ M: Laurent Pinchart L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml F: drivers/media/i2c/mt9p031.c F: include/media/i2c/mt9p031.h From patchwork Thu Jul 8 09:19:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 75630 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1m1QC3-00Fu7s-Hw; Thu, 08 Jul 2021 09:19:39 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231453AbhGHJWR (ORCPT + 1 other); Thu, 8 Jul 2021 05:22:17 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:46340 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbhGHJWK (ORCPT ); Thu, 8 Jul 2021 05:22:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1625735963; x=1628327963; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=iPCwYoZWJZV4vwThU3muuhgkMB2HBIf7o/b+oay4+PA=; b=TM+Eac0WxmL5yRDrAB8CsT7WLbMVg/57l1cY0PI6PL6vIT/ICis8ttBhyGQrE4so dfno+s5fYEKY+rGhnIylVTo4FvXmPzcdWwt1Go3TSO8tkkp2a9BgRzBW7hEHZMoE z+c+7LW/uLyJdotJOCxc/55UWEbEmHAbc7fZvdT3v+0=; X-AuditID: c39127d2-1d8f870000001daf-8a-60e6c31bbd9e Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id AA.B7.07599.B13C6E06; Thu, 8 Jul 2021 11:19:23 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021070811192355-1113446 ; Thu, 8 Jul 2021 11:19:23 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/6] media: dt-bindings: mt9p031: Add missing required properties Date: Thu, 8 Jul 2021 11:19:22 +0200 Message-Id: <20210708091922.5508-7-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708091922.5508-1-s.riedmueller@phytec.de> References: <20210708091922.5508-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 08.07.2021 11:19:23 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWyRoCBS1f68LMEg9dPzS3mHznHatE5cQm7 xeVdc9gsejZsZbVYtukPk0Xr3iPsFp+2fGNyYPeY3TGT1WPTqk42j3knAz0+b5ILYInisklJ zcksSy3St0vgyvjVtZCtoI+3YuK+g4wNjB84uxg5OSQETCRO/pjD2MXIxSEksI1RYsPvD1DO NUaJBXNbWECq2ASMJBZMa2QCSYgItDFK7DjSDOYwC2xhlJh+eTkbSJWwQIhEz5s7TCA2i4CK xJTlp9lBbF4Ba4nNG+eyQOyTl5h56TtQnIODU8BGoqs/BSQsBFRybNYtVohyQYmTM5+wgMyX ELjCKDH/1zI2iF4hidOLzzKD2MwC2hLLFr5mnsAoMAtJzywkqQWMTKsYhXIzk7NTizKz9Qoy KktSk/VSUjcxAgP48ET1SzsY++Z4HGJk4mA8xCjBwawkwms041mCEG9KYmVValF+fFFpTmrx IUZpDhYlcd4NvCVhQgLpiSWp2ampBalFMFkmDk6pBkbhvefZmHbeNN5rzBh+qWAN++Pifcxe OQkautPajKMkzbbGBzpwpP6b/kZhDntj5ZzK6JClLwWmvLqncd7FIzntXG32rDlhvd0bPm/g P7BeX/Vcd6XEHtdjW6Z91dOTmGJ5J/N1o2vgyV1TXC8tZ7e032Tb9S+kI1wl8vgq7dVr3jx1 +nnB4qMSS3FGoqEWc1FxIgB1sv9WTgIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.3 (--) X-LSpam-Report: No, score=-2.3 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,T_DKIM_INVALID=0.01 autolearn=ham autolearn_force=no Add missing required clocks and supply regulator properties for the sensor input clock and vdd, vdd_io and vaa supply regulators. Signed-off-by: Stefan Riedmueller --- .../bindings/media/i2c/aptina,mt9p031.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml index 7de62e339895..09560d97a59d 100644 --- a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml @@ -24,6 +24,18 @@ properties: description: I2C device address maxItems: 1 + clocks: + maxItems: 1 + + vdd-supply: + description: Digital supply voltage, 1.8 V + + vdd_io-supply: + description: I/O supply voltage, 1.8 or 2.8 V + + vaa-supply: + description: Analog supply voltage, 2.8 V + reset-gpios: maxItems: 1 description: Chip reset GPIO @@ -48,6 +60,10 @@ properties: required: - compatible - reg + - clocks + - vdd-supply + - vdd_io-supply + - vaa-supply - port additionalProperties: false @@ -63,6 +79,12 @@ examples: reg = <0x5d>; reset-gpios = <&gpio_sensor 0 0>; + clocks = <&sensor_clk>; + + vdd-supply = <®_vdd>; + vdd_io-supply = <®_vdd_io>; + vaa-supply = <®_vaa>; + port { mt9p031_1: endpoint { input-clock-frequency = <6000000>;