From patchwork Wed May 26 15:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74608 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvNf-005Ciz-Fd; Wed, 26 May 2021 15:23:35 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235456AbhEZPZC (ORCPT + 1 other); Wed, 26 May 2021 11:25:02 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57164 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235396AbhEZPY6 (ORCPT ); Wed, 26 May 2021 11:24:58 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNKSo076748; Wed, 26 May 2021 10:23:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042600; bh=tiiN7makazoom7pCtyD0iCir4iR2Oy+IqqShZdnezTE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I3O+BFF7WXi1/Usorz2skRjQlEDLzU/xcXlr1fe6iT2SiBznJ+9ppkUW+dCVzK5h4 l+xn9qiMsUA9v9eFVBmdDDaWaDVe7vUJmO+OJivOYJGU0N1Y3wdlFfCotQzp4LiJCl zlTfO+TjALGUe1mMVIA2C0czqvVgY2p5j3g2Srt8= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNKUI078202 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:20 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:19 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:19 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9JZ056314; Wed, 26 May 2021 10:23:15 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 01/18] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Date: Wed, 26 May 2021 20:52:51 +0530 Message-ID: <20210526152308.16525-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no From: Paul Kocialkowski As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by: Paul Kocialkowski Signed-off-by: Pratyush Yadav --- (no changes since v1) include/linux/phy/phy-mipi-dphy.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index a877ffee845d..0f57ef46a8b5 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,19 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +/** + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode + * + * A MIPI D-PHY can be used to transmit or receive data. + * Since some controllers can support both, the direction to enable is specified + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode. + */ + +enum phy_mipi_dphy_submode { + PHY_MIPI_DPHY_SUBMODE_TX = 0, + PHY_MIPI_DPHY_SUBMODE_RX, +}; + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * From patchwork Wed May 26 15:22:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74609 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvNj-005CjG-WC; Wed, 26 May 2021 15:23:40 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235473AbhEZPZJ (ORCPT + 1 other); Wed, 26 May 2021 11:25:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57222 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235458AbhEZPZE (ORCPT ); Wed, 26 May 2021 11:25:04 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNP5B076772; Wed, 26 May 2021 10:23:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042605; bh=ojmbFexRdMH8mKwkR76UTDcC9muBuXEes+AfsG/jM/k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k8E5IpBv8FGPHyaCXoqnhlfS85ncibtGSfj+02PyEw6fiUAGYLlPJebmkMl0FSNTY KTWj0Tk0AXfxrAwwkhmieiaN5wqFL9f3RJCmINUDyjRZ6bulDNAiiwH+dQPo2038Na c1iHMkSy/Jk2mqB6uSVKMFdfKsxlgVuTX2t3T7t4= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNPFw100435 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:25 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:24 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:24 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Ja056314; Wed, 26 May 2021 10:23:20 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 02/18] phy: cdns-dphy: Prepare for Rx support Date: Wed, 26 May 2021 20:52:52 +0530 Message-ID: <20210526152308.16525-3-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The Rx programming sequence differs from the Tx programming sequence. Currently only Tx mode is supported. Move all the Tx related parts into a set of Tx-specific hooks that are then called by the main PHY framework hooks. This way when Rx support is added all that is needed to be done is to plug in the Rx hooks. The clocks "psm" and "pll_ref" are not used by the Rx path so make them optional in the probe and then check if they exist in the power_on() hook. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 140 ++++++++++++++++++++++++-------- 1 file changed, 104 insertions(+), 36 deletions(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index ba042e39cfaf..8656f2102a91 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -75,6 +75,11 @@ struct cdns_dphy; struct cdns_dphy_ops { int (*probe)(struct cdns_dphy *dphy); void (*remove)(struct cdns_dphy *dphy); + int (*power_on)(struct cdns_dphy *dphy); + int (*power_off)(struct cdns_dphy *dphy); + int (*validate)(struct cdns_dphy *dphy, enum phy_mode mode, int submode, + union phy_configure_opts *opts); + int (*configure)(struct cdns_dphy *dphy, union phy_configure_opts *opts); void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, enum cdns_dphy_clk_lane_cfg cfg); @@ -86,12 +91,18 @@ struct cdns_dphy_ops { struct cdns_dphy { struct cdns_dphy_cfg cfg; void __iomem *regs; + struct device *dev; struct clk *psm_clk; struct clk *pll_ref_clk; const struct cdns_dphy_ops *ops; struct phy *phy; }; +struct cdns_dphy_driver_data { + const struct cdns_dphy_ops *tx; + const struct cdns_dphy_ops *rx; +}; + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -199,20 +210,9 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) dphy->regs + DPHY_PSM_CFG); } -/* - * This is the reference implementation of DPHY hooks. Specific integration of - * this IP may have to re-implement some of them depending on how they decided - * to wire things in the SoC. - */ -static const struct cdns_dphy_ops ref_dphy_ops = { - .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, - .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, - .set_psm_div = cdns_dphy_ref_set_psm_div, -}; - -static int cdns_dphy_config_from_opts(struct phy *phy, - struct phy_configure_opts_mipi_dphy *opts, - struct cdns_dphy_cfg *cfg) +static int cdns_dphy_tx_config_from_opts(struct phy *phy, + struct phy_configure_opts_mipi_dphy *opts, + struct cdns_dphy_cfg *cfg) { struct cdns_dphy *dphy = phy_get_drvdata(phy); unsigned int dsi_hfp_ext = 0; @@ -232,24 +232,13 @@ static int cdns_dphy_config_from_opts(struct phy *phy, return 0; } -static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, - union phy_configure_opts *opts) +static int cdns_dphy_tx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) { struct cdns_dphy_cfg cfg = { 0 }; - - if (mode != PHY_MODE_MIPI_DPHY) - return -EINVAL; - - return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); -} - -static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - struct cdns_dphy *dphy = phy_get_drvdata(phy); - struct cdns_dphy_cfg cfg = { 0 }; int ret; - ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); + ret = cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); if (ret) return ret; @@ -279,9 +268,21 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } -static int cdns_dphy_power_on(struct phy *phy) +static int cdns_dphy_tx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); + struct cdns_dphy_cfg cfg = { 0 }; + + if (submode != PHY_MIPI_DPHY_SUBMODE_TX) + return -EINVAL; + + return cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); +} + +static int cdns_dphy_tx_power_on(struct cdns_dphy *dphy) +{ + if (!dphy->psm_clk || !dphy->pll_ref_clk) + return -EINVAL; clk_prepare_enable(dphy->psm_clk); clk_prepare_enable(dphy->pll_ref_clk); @@ -293,16 +294,77 @@ static int cdns_dphy_power_on(struct phy *phy) return 0; } -static int cdns_dphy_power_off(struct phy *phy) +static int cdns_dphy_tx_power_off(struct cdns_dphy *dphy) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); - clk_disable_unprepare(dphy->pll_ref_clk); clk_disable_unprepare(dphy->psm_clk); return 0; } +static const struct cdns_dphy_ops tx_ref_dphy_ops = { + .power_on = cdns_dphy_tx_power_on, + .power_off = cdns_dphy_tx_power_off, + .validate = cdns_dphy_tx_validate, + .configure = cdns_dphy_tx_configure, + .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, + .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, + .set_psm_div = cdns_dphy_ref_set_psm_div, +}; + +/* + * This is the reference implementation of DPHY hooks. Specific integration of + * this IP may have to re-implement some of them depending on how they decided + * to wire things in the SoC. + */ +static const struct cdns_dphy_driver_data ref_dphy_ops = { + .tx = &tx_ref_dphy_ops, +}; + +static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, + union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (dphy->ops->validate) + return dphy->ops->validate(dphy, mode, submode, opts); + + return 0; +} + +static int cdns_dphy_power_on(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_on) + return dphy->ops->power_on(dphy); + + return 0; +} + +static int cdns_dphy_power_off(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_off) + return dphy->ops->power_off(dphy); + + return 0; +} + +static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->configure) + return dphy->ops->configure(dphy, opts); + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, @@ -314,14 +376,20 @@ static int cdns_dphy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct cdns_dphy *dphy; + const struct cdns_dphy_driver_data *ddata; int ret; dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); if (!dphy) return -ENOMEM; dev_set_drvdata(&pdev->dev, dphy); + dphy->dev = &pdev->dev; - dphy->ops = of_device_get_match_data(&pdev->dev); + ddata = of_device_get_match_data(&pdev->dev); + if (!ddata) + return -EINVAL; + + dphy->ops = ddata->tx; if (!dphy->ops) return -EINVAL; @@ -329,11 +397,11 @@ static int cdns_dphy_probe(struct platform_device *pdev) if (IS_ERR(dphy->regs)) return PTR_ERR(dphy->regs); - dphy->psm_clk = devm_clk_get(&pdev->dev, "psm"); + dphy->psm_clk = devm_clk_get_optional(dphy->dev, "psm"); if (IS_ERR(dphy->psm_clk)) return PTR_ERR(dphy->psm_clk); - dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); + dphy->pll_ref_clk = devm_clk_get_optional(dphy->dev, "pll_ref"); if (IS_ERR(dphy->pll_ref_clk)) return PTR_ERR(dphy->pll_ref_clk); From patchwork Wed May 26 15:22:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74610 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvNm-005CjW-6Z; Wed, 26 May 2021 15:23:42 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232692AbhEZPZL (ORCPT + 1 other); Wed, 26 May 2021 11:25:11 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59196 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235470AbhEZPZJ (ORCPT ); Wed, 26 May 2021 11:25:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNUZL001547; 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Wed, 26 May 2021 10:23:30 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jb056314; Wed, 26 May 2021 10:23:25 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 03/18] phy: cdns-dphy: Allow setting mode Date: Wed, 26 May 2021 20:52:53 +0530 Message-ID: <20210526152308.16525-4-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Allow callers to set the PHY mode. The main mode should always be PHY_MODE_MIPI_DPHY but the submode can either be PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops based on the requested submode. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 8656f2102a91..7d5f7b333893 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -365,11 +365,41 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } +static int cdns_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + const struct cdns_dphy_driver_data *ddata; + + ddata = of_device_get_match_data(dphy->dev); + if (!ddata) + return -EINVAL; + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (submode == PHY_MIPI_DPHY_SUBMODE_TX) { + if (!ddata->tx) + return -EOPNOTSUPP; + + dphy->ops = ddata->tx; + } else if (submode == PHY_MIPI_DPHY_SUBMODE_RX) { + if (!ddata->rx) + return -EOPNOTSUPP; + + dphy->ops = ddata->rx; + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, .power_on = cdns_dphy_power_on, .power_off = cdns_dphy_power_off, + .set_mode = cdns_dphy_set_mode, }; static int cdns_dphy_probe(struct platform_device *pdev) From patchwork Wed May 26 15:22:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74611 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvNw-005Ck2-QI; Wed, 26 May 2021 15:23:53 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235504AbhEZPZV (ORCPT + 1 other); Wed, 26 May 2021 11:25:21 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57254 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235470AbhEZPZP (ORCPT ); Wed, 26 May 2021 11:25:15 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNZFF076842; Wed, 26 May 2021 10:23:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042615; bh=YxJAyBuPJt+20Tmz+rFXgMt9hinHGh2Zdv4e/6trMVg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kE1KXBvci06ZjrKHbphRdCvcvyiMb775yNNyqtk8+br7g4pj/ZGB1x1hczK6+Fe+F T0C2XYZyHJS8DKznE4GXtObYmd3nzqch4mDq1UqajLN+6y9zzJqi7AarHy2Gy9RQJu yDOk5b8pSDeuSg1UqyZpUPWgCpS08BfCyk894S4w= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNZF3093354 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:35 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:35 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:35 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jc056314; Wed, 26 May 2021 10:23:30 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 04/18] phy: cdns-dphy: Add Rx support Date: Wed, 26 May 2021 20:52:54 +0530 Message-ID: <20210526152308.16525-5-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The Cadence DPHY can be used to receive image data over the CSI-2 protocol. Add support for Rx mode. The programming sequence differs from the Tx mode so it is added as a separate set of hooks to isolate the two paths. The PHY is in Tx mode by default and it needs to be set in Rx mode by setting the submode to PHY_MIPI_DPHY_SUBMODE_RX in the set_mode() callback. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 237 ++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 7d5f7b333893..7bbca679e2bb 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright: 2017-2018 Cadence Design Systems, Inc. + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include +#include #include #include #include @@ -25,10 +28,14 @@ #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) #define DPHY_PCS(reg) (0xb00 + (reg)) +#define DPHY_ISO(reg) (0xc00 + (reg)) #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) +#define DPHY_CMN_RX_MODE_EN BIT(10) +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) #define DPHY_CMN_PWM_DIV(x) ((x) << 20) @@ -45,10 +52,27 @@ #define DPHY_CMN_OPDIV_FROM_REG BIT(6) #define DPHY_CMN_OPDIV(x) ((x) << 7) +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) + #define DPHY_PSM_CFG DPHY_PCS(0x4) #define DPHY_PSM_CFG_FROM_REG BIT(0) #define DPHY_PSM_CLK_DIV(x) ((x) << 1) +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa + +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) +#define DPHY_ISO_LANE_READY_BIT 0 +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL + #define DSI_HBP_FRAME_OVERHEAD 12 #define DSI_HSA_FRAME_OVERHEAD 14 #define DSI_HFP_FRAME_OVERHEAD 6 @@ -57,6 +81,9 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 +#define DPHY_LANES_MIN 1 +#define DPHY_LANES_MAX 4 + struct cdns_dphy_cfg { u8 pll_ipdiv; u8 pll_opdiv; @@ -312,6 +339,214 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { .set_psm_div = cdns_dphy_ref_set_psm_div, }; +static int cdns_dphy_rx_power_on(struct cdns_dphy *dphy) +{ + /* Start RX state machine. */ + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, + DPHY_CMN_RX_BANDGAP_TIMER), + dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_power_off(struct cdns_dphy *dphy) +{ + writel(0, dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate = hs_clk_rate / 1000000UL; + + if (rate < 80 || rate >= 2500) + return -EOPNOTSUPP; + + if (rate >= 80 && rate < 100) + return 0; + + if (rate >= 100 && rate < 120) + return 1; + + if (rate >= 120 && rate < 160) + return 2; + + if (rate >= 160 && rate < 200) + return 3; + + if (rate >= 200 && rate < 240) + return 4; + + if (rate >= 240 && rate < 280) + return 5; + + if (rate >= 280 && rate < 320) + return 6; + + if (rate >= 320 && rate < 360) + return 7; + + if (rate >= 360 && rate < 400) + return 8; + + if (rate >= 400 && rate < 480) + return 9; + + if (rate >= 480 && rate < 560) + return 10; + + if (rate >= 560 && rate < 640) + return 11; + + if (rate >= 640 && rate < 720) + return 12; + + if (rate >= 720 && rate < 800) + return 13; + + if (rate >= 800 && rate < 880) + return 14; + + if (rate >= 880 && rate < 1040) + return 15; + + if (rate >= 1040 && rate < 1200) + return 16; + + if (rate >= 1200 && rate < 1350) + return 17; + + if (rate >= 1350 && rate < 1500) + return 18; + + if (rate >= 1500 && rate < 1750) + return 19; + + if (rate >= 1750 && rate < 2000) + return 20; + + if (rate >= 2000 && rate < 2250) + return 21; + + if (rate >= 2250 && rate < 2500) + return 22; + + /* Unreachable. */ + WARN(1, "Reached unreachable code."); + return -EINVAL; +} + +static int cdns_dphy_rx_wait_for_bit(void __iomem *addr, unsigned int bit) +{ + u32 val; + + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); +} + +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy *dphy, int lanes) +{ + void __iomem *reg = dphy->regs; + int ret; + + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) + return -EINVAL; + + /* Clock lane */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + /* Data lanes. Minimum one lane is mandatory. */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L0, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 2) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L1, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 3) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L2, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 4) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L3, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + return 0; +} + +static int cdns_dphy_rx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) +{ + unsigned int reg; + int band_ctrl, ret; + + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + + /* + * Set the required power island phase 2 time. This is mandated by DPHY + * specs. + */ + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); + + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); + if (ret) { + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + int ret; + + if (submode != PHY_MIPI_DPHY_SUBMODE_RX) + return -EINVAL; + + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (ret < 0) + return ret; + + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); +} + +static const struct cdns_dphy_ops rx_ref_dphy_ops = { + .power_on = cdns_dphy_rx_power_on, + .power_off = cdns_dphy_rx_power_off, + .configure = cdns_dphy_rx_configure, + .validate = cdns_dphy_rx_validate, +}; + /* * This is the reference implementation of DPHY hooks. Specific integration of * this IP may have to re-implement some of them depending on how they decided @@ -319,6 +554,7 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { */ static const struct cdns_dphy_driver_data ref_dphy_ops = { .tx = &tx_ref_dphy_ops, + .rx = &rx_ref_dphy_ops, }; static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, @@ -483,5 +719,6 @@ static struct platform_driver cdns_dphy_platform_driver = { module_platform_driver(cdns_dphy_platform_driver); MODULE_AUTHOR("Maxime Ripard "); +MODULE_AUTHOR("Pratyush Yadav "); MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver"); MODULE_LICENSE("GPL"); From patchwork Wed May 26 15:22:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74612 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvO3-005Ck2-OM; Wed, 26 May 2021 15:24:01 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235396AbhEZPZ3 (ORCPT + 1 other); Wed, 26 May 2021 11:25:29 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57266 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235507AbhEZPZ0 (ORCPT ); Wed, 26 May 2021 11:25:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNeHt076862; Wed, 26 May 2021 10:23:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042620; bh=W9KtbhWc69uFW7TWtNV1CvIGGgRjw1aPelfSIlmtk3k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BkGYJ3+bQW2YTFj1iMj9YPRtjxTYbX+9sNeZCVqwyDvmPwAYmueKYpk+y3P+r/ZFn 2yRflgihVz7KMTzL3OmwHNNLY3eKRC3fQhfnVupQ3LVTwY+gOl1FU4qde1QkCcxS0a Qty/V8mqyCU40PVxEPGoO9BTKtLUXcJvLKlHczI4= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNebX093422 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:40 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:40 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:40 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jd056314; Wed, 26 May 2021 10:23:35 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 05/18] media: ov5640: Use runtime PM to control sensor power Date: Wed, 26 May 2021 20:52:55 +0530 Message-ID: <20210526152308.16525-6-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Calling s_power subdev callback is discouraged. Instead, the subdevs should use runtime PM to control its power. Use runtime PM callbacks to control sensor power. The pm counter is incremented when the stream is started and decremented when the stream is stopped. Refactor s_stream() a bit to make this new control flow easier. Add a helper to choose whether mipi or dvp set_stream needs to be called. The logic flow is also changed to make it a bit clearer. Signed-off-by: Pratyush Yadav --- Changes in v2: - New in v2. drivers/media/i2c/Kconfig | 2 +- drivers/media/i2c/ov5640.c | 124 +++++++++++++++++++++++-------------- 2 files changed, 77 insertions(+), 49 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 462c0e059754..5588fc1cc14a 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -914,7 +914,7 @@ config VIDEO_OV2740 config VIDEO_OV5640 tristate "OmniVision OV5640 sensor support" - depends on OF + depends on OF && PM depends on GPIOLIB && VIDEO_V4L2 && I2C select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index 5b9cc71df473..4ed5758e2398 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -238,8 +239,6 @@ struct ov5640_dev { /* lock to protect all members below */ struct mutex lock; - int power_count; - struct v4l2_mbus_framefmt fmt; bool pending_fmt_change; @@ -1277,6 +1276,14 @@ static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on) on ? 0x00 : 0x0f); } +static int ov5640_set_stream(struct ov5640_dev *sensor, bool on) +{ + if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) + return ov5640_set_stream_mipi(sensor, on); + else + return ov5640_set_stream_dvp(sensor, on); +} + static int ov5640_get_sysclk(struct ov5640_dev *sensor) { /* calculate sysclk */ @@ -2155,37 +2162,6 @@ static int ov5640_set_power(struct ov5640_dev *sensor, bool on) /* --------------- Subdev Operations --------------- */ -static int ov5640_s_power(struct v4l2_subdev *sd, int on) -{ - struct ov5640_dev *sensor = to_ov5640_dev(sd); - int ret = 0; - - mutex_lock(&sensor->lock); - - /* - * If the power count is modified from 0 to != 0 or from != 0 to 0, - * update the power state. - */ - if (sensor->power_count == !on) { - ret = ov5640_set_power(sensor, !!on); - if (ret) - goto out; - } - - /* Update the power count. */ - sensor->power_count += on ? 1 : -1; - WARN_ON(sensor->power_count < 0); -out: - mutex_unlock(&sensor->lock); - - if (on && !ret && sensor->power_count == 1) { - /* restore controls */ - ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler); - } - - return ret; -} - static int ov5640_try_frame_interval(struct ov5640_dev *sensor, struct v4l2_fract *fi, u32 width, u32 height) @@ -2681,6 +2657,7 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = ctrl_to_sd(ctrl); struct ov5640_dev *sensor = to_ov5640_dev(sd); + struct device *dev = &sensor->i2c_client->dev; int ret; /* v4l2_ctrl_lock() locks our own mutex */ @@ -2690,7 +2667,7 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl) * not apply any controls to H/W at this time. Instead * the controls will be restored right after power-up. */ - if (sensor->power_count == 0) + if (pm_runtime_suspended(dev)) return 0; switch (ctrl->id) { @@ -2939,39 +2916,56 @@ static int ov5640_enum_mbus_code(struct v4l2_subdev *sd, static int ov5640_s_stream(struct v4l2_subdev *sd, int enable) { struct ov5640_dev *sensor = to_ov5640_dev(sd); + struct device *dev = &sensor->i2c_client->dev; int ret = 0; mutex_lock(&sensor->lock); - if (sensor->streaming == !enable) { - if (enable && sensor->pending_mode_change) { + if (sensor->streaming == enable) + goto out; + + if (enable) { + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto out; + } + + if (sensor->pending_mode_change) { ret = ov5640_set_mode(sensor); if (ret) - goto out; + goto put_pm; } - if (enable && sensor->pending_fmt_change) { + if (sensor->pending_fmt_change) { ret = ov5640_set_framefmt(sensor, &sensor->fmt); if (ret) - goto out; + goto put_pm; sensor->pending_fmt_change = false; } - if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) - ret = ov5640_set_stream_mipi(sensor, enable); - else - ret = ov5640_set_stream_dvp(sensor, enable); + ret = ov5640_set_stream(sensor, enable); + if (ret) + goto put_pm; + } else { + ret = ov5640_set_stream(sensor, enable); + if (ret) + goto out; - if (!ret) - sensor->streaming = enable; + pm_runtime_put(dev); } + + sensor->streaming = enable; + goto out; + +put_pm: + pm_runtime_put(dev); out: mutex_unlock(&sensor->lock); return ret; } static const struct v4l2_subdev_core_ops ov5640_core_ops = { - .s_power = ov5640_s_power, .log_status = v4l2_ctrl_subdev_log_status, .subscribe_event = v4l2_ctrl_subdev_subscribe_event, .unsubscribe_event = v4l2_event_subdev_unsubscribe, @@ -3037,6 +3031,29 @@ static int ov5640_check_chip_id(struct ov5640_dev *sensor) return ret; } +static int ov5640_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5640_dev *sensor = to_ov5640_dev(subdev); + + return ov5640_set_power(sensor, false); +} + +static int ov5640_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5640_dev *sensor = to_ov5640_dev(subdev); + int ret = 0; + + ret = ov5640_set_power(sensor, true); + if (ret) + return ret; + + return __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); +} + static int ov5640_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -3162,13 +3179,17 @@ static int ov5640_probe(struct i2c_client *client) if (ret) goto entity_cleanup; + pm_runtime_enable(dev); + pm_runtime_set_suspended(dev); + ret = v4l2_async_register_subdev_sensor(&sensor->sd); if (ret) - goto free_ctrls; + goto error_pm; return 0; -free_ctrls: +error_pm: + pm_runtime_disable(dev); v4l2_ctrl_handler_free(&sensor->ctrls.handler); entity_cleanup: media_entity_cleanup(&sensor->sd.entity); @@ -3178,17 +3199,23 @@ static int ov5640_probe(struct i2c_client *client) static int ov5640_remove(struct i2c_client *client) { + struct device *dev = &client->dev; struct v4l2_subdev *sd = i2c_get_clientdata(client); struct ov5640_dev *sensor = to_ov5640_dev(sd); v4l2_async_unregister_subdev(&sensor->sd); media_entity_cleanup(&sensor->sd.entity); + pm_runtime_disable(dev); v4l2_ctrl_handler_free(&sensor->ctrls.handler); mutex_destroy(&sensor->lock); return 0; } +static const struct dev_pm_ops ov5640_pm_ops = { + SET_RUNTIME_PM_OPS(ov5640_suspend, ov5640_resume, NULL) +}; + static const struct i2c_device_id ov5640_id[] = { {"ov5640", 0}, {}, @@ -3205,6 +3232,7 @@ static struct i2c_driver ov5640_i2c_driver = { .driver = { .name = "ov5640", .of_match_table = ov5640_dt_ids, + .pm = &ov5640_pm_ops, }, .id_table = ov5640_id, .probe_new = ov5640_probe, From patchwork Wed May 26 15:22:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74613 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvO5-005Ck2-RR; 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Wed, 26 May 2021 10:23:45 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:45 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:45 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Je056314; Wed, 26 May 2021 10:23:40 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 06/18] media: cadence: csi2rx: Add external DPHY support Date: Wed, 26 May 2021 20:52:56 +0530 Message-ID: <20210526152308.16525-7-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Some platforms like TI's J721E can have the CSI2RX paired with an external DPHY. Add support to enable and configure the DPHY using the generic PHY framework. Get the pixel rate and bpp from the subdev and pass them on to the DPHY along with the number of lanes. All other settings are left to their default values. Signed-off-by: Pratyush Yadav --- Changes in v2: - Use phy_pm_runtime_get_sync() and phy_pm_runtime_put() before making calls to set PHY mode, etc. to make sure it is ready. drivers/media/platform/cadence/cdns-csi2rx.c | 158 +++++++++++++++++-- 1 file changed, 148 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index c68a3eac62cd..459326de2eff 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -30,6 +30,12 @@ #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) +#define CSI2RX_DPHY_LANE_CTRL_REG 0x40 +#define CSI2RX_DPHY_CL_RST BIT(16) +#define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12) +#define CSI2RX_DPHY_CL_EN BIT(4) +#define CSI2RX_DPHY_DL_EN(i) BIT(i) + #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) @@ -54,6 +60,11 @@ enum csi2rx_pads { CSI2RX_PAD_MAX, }; +struct csi2rx_fmt { + u32 code; + u8 bpp; +}; + struct csi2rx_priv { struct device *dev; unsigned int count; @@ -85,6 +96,52 @@ struct csi2rx_priv { int source_pad; }; +static const struct csi2rx_fmt formats[] = { + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .bpp = 16, + }, +}; + +static u8 csi2rx_get_bpp(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + if (formats[i].code == code) + return formats[i].bpp; + } + + return 0; +} + +static s64 csi2rx_get_pixel_rate(struct csi2rx_priv *csi2rx) +{ + struct v4l2_ctrl *ctrl; + + ctrl = v4l2_ctrl_find(csi2rx->source_subdev->ctrl_handler, + V4L2_CID_PIXEL_RATE); + if (!ctrl) { + dev_err(csi2rx->dev, "no pixel rate control in subdev: %s\n", + csi2rx->source_subdev->name); + return -EINVAL; + } + + return v4l2_ctrl_g_ctrl_int64(ctrl); +} + static inline struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) { @@ -101,6 +158,66 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); } +static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) +{ + union phy_configure_opts opts = { }; + struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; + struct v4l2_subdev_format sd_fmt; + s64 pixel_rate; + int ret; + u8 bpp; + bool got_pm = true; + + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + sd_fmt.pad = 0; + + ret = v4l2_subdev_call(csi2rx->source_subdev, pad, get_fmt, NULL, + &sd_fmt); + if (ret) + return ret; + + bpp = csi2rx_get_bpp(sd_fmt.format.code); + if (!bpp) + return -EINVAL; + + pixel_rate = csi2rx_get_pixel_rate(csi2rx); + if (pixel_rate < 0) + return pixel_rate; + + ret = phy_mipi_dphy_get_default_config(pixel_rate, bpp, + csi2rx->num_lanes, cfg); + if (ret) + return ret; + + ret = phy_pm_runtime_get_sync(csi2rx->dphy); + if (ret == -ENOTSUPP) + got_pm = false; + else if (ret) + return ret; + + ret = phy_set_mode_ext(csi2rx->dphy, PHY_MODE_MIPI_DPHY, + PHY_MIPI_DPHY_SUBMODE_RX); + if (ret) + goto out; + + ret = phy_power_on(csi2rx->dphy); + if (ret) + goto out; + + ret = phy_configure(csi2rx->dphy, &opts); + if (ret) { + /* Can't do anything if it fails. Ignore the return value. */ + phy_power_off(csi2rx->dphy); + goto out; + } + +out: + if (got_pm) + phy_pm_runtime_put(csi2rx->dphy); + + return ret; +} + static int csi2rx_start(struct csi2rx_priv *csi2rx) { unsigned int i; @@ -139,6 +256,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pclk; + /* Enable DPHY clk and data lanes. */ + if (csi2rx->dphy) { + reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; + for (i = 0; i < csi2rx->num_lanes; i++) { + reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); + reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); + } + + writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + } + /* * Create a static mapping between the CSI virtual channels * and the output stream. @@ -169,10 +297,21 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pixclk; + if (csi2rx->dphy) { + ret = csi2rx_configure_external_dphy(csi2rx); + if (ret) { + dev_err(csi2rx->dev, + "Failed to configure external DPHY: %d\n", ret); + goto err_disable_sysclk; + } + } + clk_disable_unprepare(csi2rx->p_clk); return 0; +err_disable_sysclk: + clk_disable_unprepare(csi2rx->sys_clk); err_disable_pixclk: for (; i > 0; i--) clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); @@ -200,6 +339,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); + + if (csi2rx->dphy) { + writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + + if (phy_power_off(csi2rx->dphy)) + dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); + } } static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) @@ -306,15 +452,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, return PTR_ERR(csi2rx->dphy); } - /* - * FIXME: Once we'll have external D-PHY support, the check - * will need to be removed. - */ - if (csi2rx->dphy) { - dev_err(&pdev->dev, "External D-PHY not supported yet\n"); - return -EINVAL; - } - clk_prepare_enable(csi2rx->p_clk); dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); clk_disable_unprepare(csi2rx->p_clk); @@ -339,7 +476,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, * FIXME: Once we'll have internal D-PHY support, the check * will need to be removed. */ - if (csi2rx->has_internal_dphy) { + if (!csi2rx->dphy && csi2rx->has_internal_dphy) { dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); return -EINVAL; } @@ -460,6 +597,7 @@ static int csi2rx_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, + csi2rx->dphy ? "external" : csi2rx->has_internal_dphy ? "internal" : "no"); return 0; From patchwork Wed May 26 15:22:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74614 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvO7-005Ck2-5N; Wed, 26 May 2021 15:24:03 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235493AbhEZPZc (ORCPT + 1 other); Wed, 26 May 2021 11:25:32 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57286 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235448AbhEZPZa (ORCPT ); Wed, 26 May 2021 11:25:30 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNpY3076891; Wed, 26 May 2021 10:23:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042631; bh=pa6nQIVZcdm7Nv79anocZJUgCF885/mvEjU3jtVZ7kU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=htWtkJbU9DTXY9r65ZK8WChykbFkmIjf2KJDahZz5GJlEWVktn7Tsj1eVbyyTH0A/ qPFSbuwUjvwzDmokigqgDNTgp+HtTPtljMGIEvhq+u2T9s9ZdQm/ZdynGWGEKiMZg/ rl8+X3F9kJX0G3Z9+GWDw+N3IkK843TE7F9228pQ= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNpw6078777 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:51 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:50 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:50 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jf056314; Wed, 26 May 2021 10:23:45 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 07/18] media: cadence: csi2rx: Soft reset the streams before starting capture Date: Wed, 26 May 2021 20:52:57 +0530 Message-ID: <20210526152308.16525-8-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 459326de2eff..80a50284e525 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -150,12 +151,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) From patchwork Wed May 26 15:22:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74615 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvOJ-005Clj-Np; Wed, 26 May 2021 15:24:16 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235350AbhEZPZo (ORCPT + 1 other); Wed, 26 May 2021 11:25:44 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59266 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235513AbhEZPZg (ORCPT ); Wed, 26 May 2021 11:25:36 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNunq001704; Wed, 26 May 2021 10:23:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042636; bh=MFL5nY0y6CtYd/l61tkEPdZ0D1+8IVPL7aElz6EnMA4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Uj9INjn22b1rqgbeLtJpFsN1fLD8onrYCL+xdViu8Y89oX1UqIFUW4pTq7faeiWpc MyladMF6n1mHhI4REQhWxCv0mHyqLNFxIXtVcK0+tJB/6eWHb9tpGA8kcrPGBgqTm9 M0mC68JYwqIZnSAzQFtkfe8DlSW+CkgOClH08gnE= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNu5J115312 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:56 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:55 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:55 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jg056314; Wed, 26 May 2021 10:23:51 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 08/18] media: cadence: csi2rx: Set the STOP bit when stopping a stream Date: Wed, 26 May 2021 20:52:58 +0530 Message-ID: <20210526152308.16525-9-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The stream stop procedure says that the STOP bit should be set when the stream is to be stopped, and then the ready bit in stream status register polled to make sure the STOP operation is finished. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 80a50284e525..ecc43a618c34 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,8 +41,12 @@ #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) #define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) +#define CSI2RX_STREAM_CTRL_STOP BIT(1) #define CSI2RX_STREAM_CTRL_START BIT(0) +#define CSI2RX_STREAM_STATUS_REG(n) (CSI2RX_STREAM_BASE(n) + 0x004) +#define CSI2RX_STREAM_STATUS_RDY BIT(31) + #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) @@ -336,12 +341,23 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) static void csi2rx_stop(struct csi2rx_priv *csi2rx) { unsigned int i; + u32 val; + int ret; clk_prepare_enable(csi2rx->p_clk); clk_disable_unprepare(csi2rx->sys_clk); for (i = 0; i < csi2rx->max_streams; i++) { - writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + writel(CSI2RX_STREAM_CTRL_STOP, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + + ret = readl_relaxed_poll_timeout(csi2rx->base + + CSI2RX_STREAM_STATUS_REG(i), + val, + (val & CSI2RX_STREAM_STATUS_RDY), + 10, 10000); + if (ret) + dev_warn(csi2rx->dev, "Failed to stop stream%d\n", i); clk_disable_unprepare(csi2rx->pixel_clk[i]); } From patchwork Wed May 26 15:22:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74616 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvOL-005Clj-87; Wed, 26 May 2021 15:24:17 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235566AbhEZPZq (ORCPT + 1 other); Wed, 26 May 2021 11:25:46 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59280 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235540AbhEZPZk (ORCPT ); Wed, 26 May 2021 11:25:40 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFO1Mt001716; Wed, 26 May 2021 10:24:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042641; bh=+Fnp8KoXJxyvVWGYh0lljVtokCpVdrXxDej3meTiGfw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lpKrBIXkngD4dYPvXBY1iierWocjKGHP8C1YbaD2xHxBoOpT7eirqz7jv1ojO2h3l Y8xUIIdtHEv9n6FN1VxHJFsqzcPym+bWNvTC3LZERekREpOvpxN+BDlWcFbVM5cpW2 jnLIOfN0h1sylUFnFdnRQPXAwmy5ZF5lsqhf03cI= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFO1OL115377 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:01 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:00 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:00 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jh056314; Wed, 26 May 2021 10:23:56 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 09/18] media: cadence: csi2rx: Fix stream data configuration Date: Wed, 26 May 2021 20:52:59 +0530 Message-ID: <20210526152308.16525-10-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register. Bit 31 is part of the VL_SELECT field. Remove it completely. Secondly, it makes little sense to enable ith virtual channel for ith stream. Sure, there might be a use-case that demands it. But there might also be a use case that demands all streams to use the 0th virtual channel. Prefer this case over the former because it is less arbitrary and also makes it very clear what the limitations of the current driver is instead of giving a false impression that multiple virtual channels are supported. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index ecc43a618c34..1df21f462f3c 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -48,7 +48,6 @@ #define CSI2RX_STREAM_STATUS_RDY BIT(31) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) -#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) @@ -301,8 +300,11 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); - writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | - CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), + /* + * Enable one virtual channel. When multiple virtual channels + * are supported this will have to be changed. + */ + writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0), csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); writel(CSI2RX_STREAM_CTRL_START, From patchwork Wed May 26 15:23:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74617 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvOh-005Cmu-DC; Wed, 26 May 2021 15:24:39 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235548AbhEZP0I (ORCPT + 1 other); Wed, 26 May 2021 11:26:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57326 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235445AbhEZPZo (ORCPT ); Wed, 26 May 2021 11:25:44 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFO614076951; Wed, 26 May 2021 10:24:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042646; bh=y47ptFTk8aLjiI5AFBqywGcPhDmxzelrkQcv54bfk3A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OXr+bS8a/T10qsBSE5NKV0OYgjnsLiCYN8KX0lLiiufvzApJhumI4PKtyjetLxxJJ +ijciwbp6QAef/Xm9kOY5mJMgBN6g/KTrNIYOIyO2GbBJ0xJORCUKNyNbcBXLDhioM R5CkEhFfsYr1xukjAzsQWxFxUtkEYp+8JCN7p+Mo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFO6Jr079220 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:06 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:06 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:06 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Ji056314; Wed, 26 May 2021 10:24:01 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 10/18] media: cadence: csi2rx: Populate subdev devnode Date: Wed, 26 May 2021 20:53:00 +0530 Message-ID: <20210526152308.16525-11-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The devnode can be used by media-ctl and other userspace tools to perform configurations on the subdev. Without it, media-ctl returns ENOENT when setting format on the sensor subdev. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 1df21f462f3c..49bed63d5faa 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -613,6 +613,7 @@ static int csi2rx_probe(struct platform_device *pdev) csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; for (i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; + csi2rx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, csi2rx->pads); From patchwork Wed May 26 15:23:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74623 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvPG-005Con-59; Wed, 26 May 2021 15:25:14 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235372AbhEZP0n (ORCPT + 1 other); Wed, 26 May 2021 11:26:43 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59298 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235522AbhEZP0T (ORCPT ); Wed, 26 May 2021 11:26:19 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOBEt001745; Wed, 26 May 2021 10:24:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042651; bh=BMdz5PIJ0bDUzRjPQ3h1Ef4Vn0+hXXShPYDakbVNwWY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LKyZ1j1jo5rtIHOGp+W2Y09byBc3lfx05EF4zJS7YJIbAfGP6NBpjQqRsSPEXDZNj vZpv13I3KS/chm0DPrdYI2k3Rdzs8nY4SWzcBHUHkhnd18wFymedxaefQVTd0LXPW5 X95OJkP55aYdSXQlbNSbGmOtTnlsOw71Ibd9Xd/k= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFOB2t101445 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:11 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:11 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jj056314; Wed, 26 May 2021 10:24:06 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 11/18] dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX Date: Wed, 26 May 2021 20:53:01 +0530 Message-ID: <20210526152308.16525-12-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can have up to 32 threads but the current driver only supports using one. So add an entry for that one thread. Signed-off-by: Pratyush Yadav --- Changes in v2: - Add all 64 threads, instead of having only the one thread being currently used by the driver. drivers/dma/ti/k3-psil-j721e.c | 73 ++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c index 7580870ed746..34e3fc565a37 100644 --- a/drivers/dma/ti/k3-psil-j721e.c +++ b/drivers/dma/ti/k3-psil-j721e.c @@ -58,6 +58,14 @@ }, \ } +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ static struct psil_ep j721e_src_ep_map[] = { /* SA2UL */ @@ -138,6 +146,71 @@ static struct psil_ep j721e_src_ep_map[] = { PSIL_PDMA_XY_PKT(0x4707), PSIL_PDMA_XY_PKT(0x4708), PSIL_PDMA_XY_PKT(0x4709), + /* CSI2RX */ + PSIL_CSI2RX(0x4940), + PSIL_CSI2RX(0x4941), + PSIL_CSI2RX(0x4942), + PSIL_CSI2RX(0x4943), + PSIL_CSI2RX(0x4944), + PSIL_CSI2RX(0x4945), + PSIL_CSI2RX(0x4946), + PSIL_CSI2RX(0x4947), + PSIL_CSI2RX(0x4948), + PSIL_CSI2RX(0x4949), + PSIL_CSI2RX(0x494a), + PSIL_CSI2RX(0x494b), + PSIL_CSI2RX(0x494c), + PSIL_CSI2RX(0x494d), + PSIL_CSI2RX(0x494e), + PSIL_CSI2RX(0x494f), + PSIL_CSI2RX(0x4950), + PSIL_CSI2RX(0x4951), + PSIL_CSI2RX(0x4952), + PSIL_CSI2RX(0x4953), + PSIL_CSI2RX(0x4954), + PSIL_CSI2RX(0x4955), + PSIL_CSI2RX(0x4956), + PSIL_CSI2RX(0x4957), + PSIL_CSI2RX(0x4958), + PSIL_CSI2RX(0x4959), + PSIL_CSI2RX(0x495a), + PSIL_CSI2RX(0x495b), + PSIL_CSI2RX(0x495c), + PSIL_CSI2RX(0x495d), + PSIL_CSI2RX(0x495e), + PSIL_CSI2RX(0x495f), + PSIL_CSI2RX(0x4960), + PSIL_CSI2RX(0x4961), + PSIL_CSI2RX(0x4962), + PSIL_CSI2RX(0x4963), + PSIL_CSI2RX(0x4964), + PSIL_CSI2RX(0x4965), + PSIL_CSI2RX(0x4966), + PSIL_CSI2RX(0x4967), + PSIL_CSI2RX(0x4968), + PSIL_CSI2RX(0x4969), + PSIL_CSI2RX(0x496a), + PSIL_CSI2RX(0x496b), + PSIL_CSI2RX(0x496c), + PSIL_CSI2RX(0x496d), + PSIL_CSI2RX(0x496e), + PSIL_CSI2RX(0x496f), + PSIL_CSI2RX(0x4970), + PSIL_CSI2RX(0x4971), + PSIL_CSI2RX(0x4972), + PSIL_CSI2RX(0x4973), + PSIL_CSI2RX(0x4974), + PSIL_CSI2RX(0x4975), + PSIL_CSI2RX(0x4976), + PSIL_CSI2RX(0x4977), + PSIL_CSI2RX(0x4978), + PSIL_CSI2RX(0x4979), + PSIL_CSI2RX(0x497a), + PSIL_CSI2RX(0x497b), + PSIL_CSI2RX(0x497c), + PSIL_CSI2RX(0x497d), + PSIL_CSI2RX(0x497e), + PSIL_CSI2RX(0x497f), /* CPSW9 */ PSIL_ETHERNET(0x4a00), /* CPSW0 */ From patchwork Wed May 26 15:23:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74619 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvP2-005CnZ-Of; Wed, 26 May 2021 15:25:01 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235532AbhEZP03 (ORCPT + 1 other); Wed, 26 May 2021 11:26:29 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59372 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235538AbhEZP0T (ORCPT ); Wed, 26 May 2021 11:26:19 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOG0P001753; Wed, 26 May 2021 10:24:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042656; bh=Fm+hVjRUGJmwYKDMUjbdou43Vw1Zw5cGhop7i6WK2Zs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mJADvKwfSNQGntLrVQzyXdzhQgYPK85gcVyr5brT2ja4ajBfvlAvS43uC2fTLd38t CoMIpUpo+39B2+6hELvgwNKcG5xOx4rSFp4oyVX16jdUbV5mGiGJa2ElGiwTQB1tkS GIi1F0jD6RO8Z+Qt17SSCWz9wdnVgT2+7u8vApQ8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFOGxk079325 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:16 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:16 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jk056314; Wed, 26 May 2021 10:24:11 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 12/18] media: Re-structure TI platform drivers Date: Wed, 26 May 2021 20:53:02 +0530 Message-ID: <20210526152308.16525-13-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The ti-vpe/ sub-directory does not only contain the VPE-specific things. It also contains the CAL driver, which is a completely different subsystem. This is also not a good place to add new drivers for other TI platforms since they will all get mixed up. Separate the VPE and CAL parts into different sub-directories and rename the ti-vpe/ sub-directory to ti/. This is now the place where new TI platform drivers can be added. Signed-off-by: Pratyush Yadav Reviewed-by: Tomi Valkeinen --- Compile tested only. There should be no functional change. Changes in v2: - New in v2. MAINTAINERS | 3 ++- drivers/media/platform/Makefile | 2 +- drivers/media/platform/ti/Makefile | 3 +++ drivers/media/platform/ti/cal/Makefile | 3 +++ drivers/media/platform/{ti-vpe => ti/cal}/cal-camerarx.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal-video.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal.h | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal_regs.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/Makefile | 4 ---- drivers/media/platform/{ti-vpe => ti/vpe}/csc.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/csc.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc_coeff.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma_priv.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpe.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpe_regs.h | 0 20 files changed, 9 insertions(+), 6 deletions(-) create mode 100644 drivers/media/platform/ti/Makefile create mode 100644 drivers/media/platform/ti/cal/Makefile rename drivers/media/platform/{ti-vpe => ti/cal}/cal-camerarx.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal-video.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal.h (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal_regs.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/Makefile (78%) rename drivers/media/platform/{ti-vpe => ti/vpe}/csc.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/csc.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc_coeff.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma_priv.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpe.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpe_regs.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 710203d794d7..607dd5e18e7d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18449,7 +18449,8 @@ W: http://linuxtv.org/ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: Documentation/devicetree/bindings/media/ti,cal.yaml F: Documentation/devicetree/bindings/media/ti,vpe.yaml -F: drivers/media/platform/ti-vpe/ +F: drivers/media/platform/ti/cal/ +F: drivers/media/platform/ti/vpe/ TI WILINK WIRELESS DRIVERS L: linux-wireless@vger.kernel.org diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index eedc14aafb32..5ddfa5bc02e1 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_VIU) += fsl-viu.o -obj-y += ti-vpe/ +obj-y += ti/ obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o obj-$(CONFIG_VIDEO_CODA) += coda/ diff --git a/drivers/media/platform/ti/Makefile b/drivers/media/platform/ti/Makefile new file mode 100644 index 000000000000..bbc737ccbbea --- /dev/null +++ b/drivers/media/platform/ti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y += cal/ +obj-y += vpe/ diff --git a/drivers/media/platform/ti/cal/Makefile b/drivers/media/platform/ti/cal/Makefile new file mode 100644 index 000000000000..45ac35585f0b --- /dev/null +++ b/drivers/media/platform/ti/cal/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_TI_CAL) += ti-cal.o +ti-cal-y := cal.o cal-camerarx.o cal-video.o diff --git a/drivers/media/platform/ti-vpe/cal-camerarx.c b/drivers/media/platform/ti/cal/cal-camerarx.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal-camerarx.c rename to drivers/media/platform/ti/cal/cal-camerarx.c diff --git a/drivers/media/platform/ti-vpe/cal-video.c b/drivers/media/platform/ti/cal/cal-video.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal-video.c rename to drivers/media/platform/ti/cal/cal-video.c diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti/cal/cal.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal.c rename to drivers/media/platform/ti/cal/cal.c diff --git a/drivers/media/platform/ti-vpe/cal.h b/drivers/media/platform/ti/cal/cal.h similarity index 100% rename from drivers/media/platform/ti-vpe/cal.h rename to drivers/media/platform/ti/cal/cal.h diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti/cal/cal_regs.h similarity index 100% rename from drivers/media/platform/ti-vpe/cal_regs.h rename to drivers/media/platform/ti/cal/cal_regs.h diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti/vpe/Makefile similarity index 78% rename from drivers/media/platform/ti-vpe/Makefile rename to drivers/media/platform/ti/vpe/Makefile index ad624056e039..3fadfe084f87 100644 --- a/drivers/media/platform/ti-vpe/Makefile +++ b/drivers/media/platform/ti/vpe/Makefile @@ -10,7 +10,3 @@ ti-sc-y := sc.o ti-csc-y := csc.o ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG - -obj-$(CONFIG_VIDEO_TI_CAL) += ti-cal.o - -ti-cal-y := cal.o cal-camerarx.o cal-video.o diff --git a/drivers/media/platform/ti-vpe/csc.c b/drivers/media/platform/ti/vpe/csc.c similarity index 100% rename from drivers/media/platform/ti-vpe/csc.c rename to drivers/media/platform/ti/vpe/csc.c diff --git a/drivers/media/platform/ti-vpe/csc.h b/drivers/media/platform/ti/vpe/csc.h similarity index 100% rename from drivers/media/platform/ti-vpe/csc.h rename to drivers/media/platform/ti/vpe/csc.h diff --git a/drivers/media/platform/ti-vpe/sc.c b/drivers/media/platform/ti/vpe/sc.c similarity index 100% rename from drivers/media/platform/ti-vpe/sc.c rename to drivers/media/platform/ti/vpe/sc.c diff --git a/drivers/media/platform/ti-vpe/sc.h b/drivers/media/platform/ti/vpe/sc.h similarity index 100% rename from drivers/media/platform/ti-vpe/sc.h rename to drivers/media/platform/ti/vpe/sc.h diff --git a/drivers/media/platform/ti-vpe/sc_coeff.h b/drivers/media/platform/ti/vpe/sc_coeff.h similarity index 100% rename from drivers/media/platform/ti-vpe/sc_coeff.h rename to drivers/media/platform/ti/vpe/sc_coeff.h diff --git a/drivers/media/platform/ti-vpe/vpdma.c b/drivers/media/platform/ti/vpe/vpdma.c similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma.c rename to drivers/media/platform/ti/vpe/vpdma.c diff --git a/drivers/media/platform/ti-vpe/vpdma.h b/drivers/media/platform/ti/vpe/vpdma.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma.h rename to drivers/media/platform/ti/vpe/vpdma.h diff --git a/drivers/media/platform/ti-vpe/vpdma_priv.h b/drivers/media/platform/ti/vpe/vpdma_priv.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma_priv.h rename to drivers/media/platform/ti/vpe/vpdma_priv.h diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti/vpe/vpe.c similarity index 100% rename from drivers/media/platform/ti-vpe/vpe.c rename to drivers/media/platform/ti/vpe/vpe.c diff --git a/drivers/media/platform/ti-vpe/vpe_regs.h b/drivers/media/platform/ti/vpe/vpe_regs.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpe_regs.h rename to drivers/media/platform/ti/vpe/vpe_regs.h From patchwork Wed May 26 15:23:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74620 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvP4-005CnZ-8d; Wed, 26 May 2021 15:25:03 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235560AbhEZP0a (ORCPT + 1 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-0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:21 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:21 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jl056314; Wed, 26 May 2021 10:24:16 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 13/18] media: ti: Add CSI2RX support for J721E Date: Wed, 26 May 2021 20:53:03 +0530 Message-ID: <20210526152308.16525-14-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The Cadence CSI2RX IP acts as a bridge between the TI specific parts and the CSI-2 protocol parts. TI then has a wrapper on top of this bridge called the SHIM layer. It takes in data from stream 0, repacks it, and sends it to memory over PSI-L DMA. This driver acts as the "front end" to V4L2 client applications. It implements the required ioctls and buffer operations, passes the necessary calls on to the bridge, programs the SHIM layer, and performs DMA via the dmaengine API to finally return the data to a buffer supplied by the application. Signed-off-by: Pratyush Yadav --- Changes in v2: - Use dmaengine_get_dma_device() instead of directly accessing dma->device->dev. - Do not set dst_addr_width when configuring slave DMA. - Move to a separate subdir and rename to j721e-csi2rx.c - Convert compatible to ti,j721e-csi2rx. - Move to use Media Controller centric APIs. - Improve cleanup in probe when one of the steps fails. - Add colorspace to formats database. - Set hw_revision on media_device. - Move video device initialization to probe time instead of register time. MAINTAINERS | 6 + drivers/media/platform/Kconfig | 12 + drivers/media/platform/ti/Makefile | 1 + .../media/platform/ti/j721e-csi2rx/Makefile | 2 + .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 884 ++++++++++++++++++ 5 files changed, 905 insertions(+) create mode 100644 drivers/media/platform/ti/j721e-csi2rx/Makefile create mode 100644 drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c diff --git a/MAINTAINERS b/MAINTAINERS index 607dd5e18e7d..2cf140a02063 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18332,6 +18332,12 @@ S: Odd Fixes F: drivers/clk/ti/ F: include/linux/clk/ti.h +TI J721E CSI2RX DRIVER +M: Pratyush Yadav +L: linux-media@vger.kernel.org +S: Supported +F: drivers/media/platform/ti/j721e-csi2rx/ + TI DAVINCI MACHINE SUPPORT M: Sekhar Nori R: Bartosz Golaszewski diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 157c924686e4..732a942b3b29 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -200,6 +200,18 @@ config VIDEO_TI_CAL_MC endif # VIDEO_TI_CAL +config VIDEO_TI_J721E_CSI2RX + tristate "TI J721E CSI2RX wrapper layer driver" + depends on VIDEO_DEV && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on MEDIA_SUPPORT && MEDIA_CONTROLLER + depends on PHY_CADENCE_DPHY && VIDEO_CADENCE_CSI2RX + depends on ARCH_K3 || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + help + Support for TI CSI2RX wrapper layer. This just enables the wrapper driver. + The Cadence CSI2RX bridge driver needs to be enabled separately. + endif # V4L_PLATFORM_DRIVERS menuconfig V4L_MEM2MEM_DRIVERS diff --git a/drivers/media/platform/ti/Makefile b/drivers/media/platform/ti/Makefile index bbc737ccbbea..17c9cfb74f66 100644 --- a/drivers/media/platform/ti/Makefile +++ b/drivers/media/platform/ti/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cal/ obj-y += vpe/ +obj-y += j721e-csi2rx/ diff --git a/drivers/media/platform/ti/j721e-csi2rx/Makefile b/drivers/media/platform/ti/j721e-csi2rx/Makefile new file mode 100644 index 000000000000..377afc1d6280 --- /dev/null +++ b/drivers/media/platform/ti/j721e-csi2rx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_TI_J721E_CSI2RX) += j721e-csi2rx.o diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c new file mode 100644 index 000000000000..b8d31a0af6d8 --- /dev/null +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -0,0 +1,884 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI CSI2 RX driver. + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author: Pratyush Yadav + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define TI_CSI2RX_MODULE_NAME "j721e-csi2rx" + +#define SHIM_CNTL 0x10 +#define SHIM_CNTL_PIX_RST BIT(0) + +#define SHIM_DMACNTX 0x20 +#define SHIM_DMACNTX_EN BIT(31) +#define SHIM_DMACNTX_YUV422 GENMASK(27, 26) +#define SHIM_DMACNTX_FMT GENMASK(5, 0) +#define SHIM_DMACNTX_UYVY 0 +#define SHIM_DMACNTX_VYUY 1 +#define SHIM_DMACNTX_YUYV 2 +#define SHIM_DMACNTX_YVYU 3 + +#define SHIM_PSI_CFG0 0x24 +#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) +#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 15) + +#define CSI_DF_YUV420 0x18 +#define CSI_DF_YUV422 0x1e +#define CSI_DF_RGB444 0x20 +#define CSI_DF_RGB888 0x24 + +#define PSIL_WORD_SIZE_BYTES 16 + +struct ti_csi2rx_fmt { + u32 fourcc; /* Four character code. */ + u32 code; /* Mbus code. */ + enum v4l2_colorspace colorspace; + u32 csi_df; /* CSI Data format. */ + u8 bpp; /* Bits per pixel. */ +}; + +struct ti_csi2rx_buffer { + /* Common v4l2 buffer. Must be first. */ + struct vb2_v4l2_buffer vb; + struct list_head list; +}; + +struct ti_csi2rx_dmaq { + struct list_head list; +}; + +struct ti_csi2rx_dev { + struct device *dev; + void __iomem *shim; + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct media_device mdev; + struct media_pipeline pipe; + struct media_pad pad; + struct v4l2_async_notifier notifier; + struct v4l2_subdev *subdev; + struct vb2_queue vidq; + struct mutex mutex; /* To serialize ioctls. */ + struct v4l2_format v_fmt; + struct dma_chan *dma; + struct ti_csi2rx_dmaq dmaq; + u32 sequence; +}; + +static const struct ti_csi2rx_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_YVYU, + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_VYUY, + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, + + /* More formats can be supported but they are not listed for now. */ +}; + +static const unsigned int num_formats = ARRAY_SIZE(formats); + +/* Forward declaration needed by ti_csi2rx_dma_callback. */ +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf); + +static const struct ti_csi2rx_fmt *find_format_by_pix(u32 pixelformat) +{ + unsigned int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].fourcc == pixelformat) + return &formats[i]; + } + + return NULL; +} + +static void ti_csi2rx_fill_fmt(const struct ti_csi2rx_fmt *csi_fmt, + struct v4l2_format *v4l2_fmt) +{ + struct v4l2_pix_format *pix = &v4l2_fmt->fmt.pix; + u32 bpl; + + v4l2_fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + pix->pixelformat = csi_fmt->fourcc; + pix->colorspace = csi_fmt->colorspace; + pix->sizeimage = pix->height * pix->width * (csi_fmt->bpp / 8); + + bpl = (pix->width * ALIGN(csi_fmt->bpp, 8)) >> 3; + pix->bytesperline = ALIGN(bpl, 16); +} + +static int ti_csi2rx_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + strscpy(cap->driver, TI_CSI2RX_MODULE_NAME, sizeof(cap->driver)); + strscpy(cap->card, TI_CSI2RX_MODULE_NAME, sizeof(cap->card)); + + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + dev_name(csi->dev)); + + return 0; +} + +static int ti_csi2rx_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index >= num_formats) + return -EINVAL; + + memset(f->reserved, 0, sizeof(f->reserved)); + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + f->pixelformat = formats[f->index].fourcc; + + return 0; +} + +static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *prov, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + *f = csi->v_fmt; + + return 0; +} + +static int ti_csi2rx_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + const struct ti_csi2rx_fmt *fmt; + + /* + * Default to the first format if the requested pixel format code isn't + * supported. + */ + fmt = find_format_by_pix(f->fmt.pix.pixelformat); + if (!fmt) + fmt = &formats[0]; + + if (f->fmt.pix.field == V4L2_FIELD_ANY) + f->fmt.pix.field = V4L2_FIELD_NONE; + + if (f->fmt.pix.field != V4L2_FIELD_NONE) + return -EINVAL; + + ti_csi2rx_fill_fmt(fmt, f); + + return 0; +} + +static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + struct vb2_queue *q = &csi->vidq; + int ret; + + if (vb2_is_busy(q)) + return -EBUSY; + + ret = ti_csi2rx_try_fmt_vid_cap(file, priv, f); + if (ret < 0) + return ret; + + csi->v_fmt = *f; + + return 0; +} + +static int ti_csi2rx_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + const struct ti_csi2rx_fmt *fmt; + u8 bpp; + + fmt = find_format_by_pix(fsize->pixel_format); + if (!fmt) + return -EINVAL; + + bpp = ALIGN(fmt->bpp, 8); + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise.min_width = PSIL_WORD_SIZE_BYTES * 8 / bpp; + fsize->stepwise.max_width = UINT_MAX; + fsize->stepwise.step_width = PSIL_WORD_SIZE_BYTES * 8 / bpp; + fsize->stepwise.min_height = 1; + fsize->stepwise.max_height = UINT_MAX; + fsize->stepwise.step_height = 1; + + return 0; +} + +static const struct v4l2_ioctl_ops csi_ioctl_ops = { + .vidioc_querycap = ti_csi2rx_querycap, + .vidioc_enum_fmt_vid_cap = ti_csi2rx_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = ti_csi2rx_try_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = ti_csi2rx_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = ti_csi2rx_s_fmt_vid_cap, + .vidioc_enum_framesizes = ti_csi2rx_enum_framesizes, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, +}; + +static const struct v4l2_file_operations csi_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, +}; + +static int ti_csi2rx_video_register(struct ti_csi2rx_dev *csi) +{ + struct video_device *vdev = &csi->vdev; + int ret, src_pad; + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) + return ret; + + src_pad = media_entity_get_fwnode_pad(&csi->subdev->entity, + csi->subdev->fwnode, + MEDIA_PAD_FL_SOURCE); + if (src_pad < 0) { + dev_err(csi->dev, "Couldn't find source pad for subdev\n"); + return src_pad; + } + + ret = media_create_pad_link(&csi->subdev->entity, src_pad, + &vdev->entity, 0, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + video_unregister_device(vdev); + return ret; + } + + return 0; +} + +static int csi_async_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + + csi->subdev = subdev; + + return 0; +} + +static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + int ret; + + ret = ti_csi2rx_video_register(csi); + if (ret) + return ret; + + return v4l2_device_register_subdev_nodes(&csi->v4l2_dev); +} + +static const struct v4l2_async_notifier_operations csi_async_notifier_ops = { + .bound = csi_async_notifier_bound, + .complete = csi_async_notifier_complete, +}; + +static int ti_csi2rx_init_subdev(struct ti_csi2rx_dev *csi) +{ + struct fwnode_handle *fwnode; + struct v4l2_async_subdev *asd; + struct device_node *node; + int ret; + + node = of_get_child_by_name(csi->dev->of_node, "csi-bridge"); + if (!node) + return -EINVAL; + + fwnode = of_fwnode_handle(node); + of_node_put(node); + if (!fwnode) + return -EINVAL; + + v4l2_async_notifier_init(&csi->notifier); + csi->notifier.ops = &csi_async_notifier_ops; + + asd = v4l2_async_notifier_add_fwnode_subdev(&csi->notifier, fwnode, + struct v4l2_async_subdev); + if (IS_ERR(asd)) { + v4l2_async_notifier_cleanup(&csi->notifier); + return PTR_ERR(asd); + } + + ret = v4l2_async_notifier_register(&csi->v4l2_dev, &csi->notifier); + if (ret) { + v4l2_async_notifier_cleanup(&csi->notifier); + return ret; + } + + return 0; +} + +static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int reg; + + fmt = find_format_by_pix(csi->v_fmt.fmt.pix.pixelformat); + if (!fmt) { + dev_err(csi->dev, "Unknown format\n"); + return; + } + + /* De-assert the pixel interface reset. */ + reg = SHIM_CNTL_PIX_RST; + writel(reg, csi->shim + SHIM_CNTL); + + reg = SHIM_DMACNTX_EN; + reg |= FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_df); + + /* + * Using the values from the documentation gives incorrect ordering for + * the luma and chroma components. In practice, the "reverse" format + * gives the correct image. So for example, if the image is in UYVY, the + * reverse would be YVYU. + */ + switch (fmt->fourcc) { + case V4L2_PIX_FMT_UYVY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YVYU); + break; + case V4L2_PIX_FMT_VYUY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YUYV); + break; + case V4L2_PIX_FMT_YUYV: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_VYUY); + break; + case V4L2_PIX_FMT_YVYU: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_UYVY); + break; + default: + /* Ignore if not YUV 4:2:2 */ + break; + } + + writel(reg, csi->shim + SHIM_DMACNTX); + + reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | + FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 1); + writel(reg, csi->shim + SHIM_PSI_CFG0); +} + +static void ti_csi2rx_dma_callback(void *param) +{ + struct ti_csi2rx_dev *csi = param; + struct ti_csi2rx_buffer *buf; + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + list_del(&buf->list); + + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.sequence = csi->sequence++; + + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + /* If there are more buffers to process then start their transfer. */ + if (list_empty(&dmaq->list)) + return; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + + if (ti_csi2rx_start_dma(csi, buf)) + dev_err(csi->dev, "Failed to queue the next buffer for DMA\n"); +} + +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf) +{ + unsigned long addr; + struct dma_async_tx_descriptor *desc; + size_t len = csi->v_fmt.fmt.pix.sizeimage; + dma_cookie_t cookie; + int ret = 0; + + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + desc = dmaengine_prep_slave_single(csi->dma, addr, len, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) + return -EIO; + + desc->callback = ti_csi2rx_dma_callback; + desc->callback_param = csi; + + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) + return ret; + + dma_async_issue_pending(csi->dma); + + return 0; +} + +static int ti_csi2rx_queue_setup(struct vb2_queue *q, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(q); + unsigned int size = csi->v_fmt.fmt.pix.sizeimage; + + if (*nplanes) { + if (sizes[0] < size) + return -EINVAL; + size = sizes[0]; + } + + *nplanes = 1; + sizes[0] = size; + + return 0; +} + +static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = csi->v_fmt.fmt.pix.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + dev_err(csi->dev, "Data will not fit into plane\n"); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + return 0; +} + +static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + struct ti_csi2rx_buffer *buf; + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + + buf = container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); + + list_add_tail(&buf->list, &dmaq->list); +} + +/* + * Find the input format. This is done by finding the first device in the + * pipeline which can tell us the current format. This could be the sensor, or + * this could be another device in the middle which is capable of format + * conversions. + */ +static int ti_csi2rx_validate_pipeline(struct ti_csi2rx_dev *csi) +{ + struct media_pipeline *pipe = &csi->pipe; + struct media_entity *entity; + struct v4l2_subdev *sd; + struct v4l2_subdev_format fmt; + struct v4l2_pix_format *pix = &csi->v_fmt.fmt.pix; + const struct ti_csi2rx_fmt *ti_fmt; + int ret; + + media_graph_walk_start(&pipe->graph, &csi->vdev.entity); + + while ((entity = media_graph_walk_next(&pipe->graph))) { + if (!is_media_entity_v4l2_subdev(entity)) + continue; + + sd = media_entity_to_v4l2_subdev(entity); + + fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.pad = media_get_pad_index(entity, 0, PAD_SIGNAL_DEFAULT); + + ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); + if (ret && ret != -ENOIOCTLCMD) + return ret; + if (!ret) + break; + } + + /* Could not find input format. */ + if (!entity) + return -EPIPE; + + if (fmt.format.width != pix->width) + return -EPIPE; + if (fmt.format.height != pix->height) + return -EPIPE; + + ti_fmt = find_format_by_pix(pix->pixelformat); + if (WARN_ON(!ti_fmt)) + return -EINVAL; + + if (fmt.format.code == MEDIA_BUS_FMT_YUYV8_2X8 || + fmt.format.code == MEDIA_BUS_FMT_VYUY8_2X8 || + fmt.format.code == MEDIA_BUS_FMT_YVYU8_2X8) { + dev_err(csi->dev, + "Only UYVY input allowed for YUV422 8-bit. Output format can be configured.\n"); + return -EPIPE; + } + + if (fmt.format.code == MEDIA_BUS_FMT_UYVY8_2X8) { + /* Format conversion between YUV422 formats can be done. */ + if (ti_fmt->code != MEDIA_BUS_FMT_UYVY8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_YUYV8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_VYUY8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_YVYU8_2X8) + return -EPIPE; + } else if (fmt.format.code != ti_fmt->code) { + return -EPIPE; + } + + if (fmt.format.field != V4L2_FIELD_NONE && + fmt.format.field != V4L2_FIELD_ANY) + return -EPIPE; + + return 0; +} + +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + struct ti_csi2rx_buffer *buf, *tmp; + int ret; + + if (list_empty(&dmaq->list)) + return -EIO; + + ret = media_pipeline_start(&csi->vdev.entity, &csi->pipe); + if (ret) + return ret; + + ret = ti_csi2rx_validate_pipeline(csi); + if (ret) { + dev_err(csi->dev, + "Format mismatch between source and video node\n"); + goto err; + } + + ti_csi2rx_setup_shim(csi); + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 1); + if (ret) + goto err; + + csi->sequence = 0; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + ret = ti_csi2rx_start_dma(csi, buf); + if (ret) { + dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + goto err_stream; + } + + return 0; + +err_stream: + v4l2_subdev_call(csi->subdev, video, s_stream, 0); +err: + media_pipeline_stop(&csi->vdev.entity); + list_for_each_entry_safe(buf, tmp, &dmaq->list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + } + + return ret; +} + +static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_buffer *buf = NULL, *tmp; + int ret; + + media_pipeline_stop(&csi->vdev.entity); + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 0); + if (ret) + dev_err(csi->dev, "Failed to stop subdev stream\n"); + + writel(0, csi->shim + SHIM_CNTL); + + ret = dmaengine_terminate_sync(csi->dma); + if (ret) + dev_err(csi->dev, "Failed to stop DMA\n"); + + writel(0, csi->shim + SHIM_DMACNTX); + + list_for_each_entry_safe(buf, tmp, &csi->dmaq.list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } +} + +static const struct vb2_ops csi_vb2_qops = { + .queue_setup = ti_csi2rx_queue_setup, + .buf_prepare = ti_csi2rx_buffer_prepare, + .buf_queue = ti_csi2rx_buffer_queue, + .start_streaming = ti_csi2rx_start_streaming, + .stop_streaming = ti_csi2rx_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) +{ + struct vb2_queue *q = &csi->vidq; + int ret; + + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; + q->drv_priv = csi; + q->buf_struct_size = sizeof(struct ti_csi2rx_buffer); + q->ops = &csi_vb2_qops; + q->mem_ops = &vb2_dma_contig_memops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->dev = dmaengine_get_dma_device(csi->dma); + q->lock = &csi->mutex; + + ret = vb2_queue_init(q); + if (ret) + return ret; + + csi->vdev.queue = q; + + return 0; +} + +static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) +{ + struct dma_slave_config cfg; + int ret; + + INIT_LIST_HEAD(&csi->dmaq.list); + + csi->dma = NULL; + + csi->dma = dma_request_chan(csi->dev, "rx0"); + if (IS_ERR(csi->dma)) + return PTR_ERR(csi->dma); + + memset(&cfg, 0, sizeof(cfg)); + + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; + + ret = dmaengine_slave_config(csi->dma, &cfg); + if (ret) + return ret; + + return 0; +} + +static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) +{ + struct media_device *mdev = &csi->mdev; + struct video_device *vdev = &csi->vdev; + int ret; + + mdev->dev = csi->dev; + mdev->hw_revision = 1; + strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); + snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", + dev_name(mdev->dev)); + + media_device_init(mdev); + + strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name)); + vdev->v4l2_dev = &csi->v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + vdev->fops = &csi_fops; + vdev->ioctl_ops = &csi_ioctl_ops; + vdev->release = video_device_release_empty; + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; + vdev->lock = &csi->mutex; + video_set_drvdata(vdev, csi); + + csi->pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&csi->vdev.entity, 1, &csi->pad); + if (ret) + return ret; + + csi->v4l2_dev.mdev = mdev; + + ret = v4l2_device_register(csi->dev, &csi->v4l2_dev); + if (ret) + return ret; + + ret = media_device_register(mdev); + if (ret) { + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(mdev); + return ret; + } + + return 0; +} + +static void ti_csi2rx_cleanup_dma(struct ti_csi2rx_dev *csi) +{ + dma_release_channel(csi->dma); +} + +static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) +{ + media_device_unregister(&csi->mdev); + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(&csi->mdev); +} + +static void ti_csi2rx_cleanup_subdev(struct ti_csi2rx_dev *csi) +{ + v4l2_async_notifier_unregister(&csi->notifier); + v4l2_async_notifier_cleanup(&csi->notifier); +} + +static void ti_csi2rx_cleanup_vb2q(struct ti_csi2rx_dev *csi) +{ + vb2_queue_release(&csi->vidq); +} + +static int ti_csi2rx_probe(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi; + struct resource *res; + int ret; + + csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); + if (!csi) + return -ENOMEM; + + csi->dev = &pdev->dev; + platform_set_drvdata(pdev, csi); + + mutex_init(&csi->mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csi->shim = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(csi->shim)) + return PTR_ERR(csi->shim); + + ret = ti_csi2rx_init_dma(csi); + if (ret) + return ret; + + ret = ti_csi2rx_v4l2_init(csi); + if (ret) + goto err_dma; + + ret = ti_csi2rx_init_vb2q(csi); + if (ret) + goto err_v4l2; + + ret = ti_csi2rx_init_subdev(csi); + if (ret) + goto err_vb2q; + + ret = of_platform_populate(csi->dev->of_node, NULL, NULL, csi->dev); + if (ret) { + dev_err(csi->dev, "Failed to create children: %d\n", ret); + goto err_subdev; + } + + return 0; + +err_subdev: + ti_csi2rx_cleanup_subdev(csi); +err_vb2q: + ti_csi2rx_cleanup_vb2q(csi); +err_v4l2: + ti_csi2rx_cleanup_v4l2(csi); +err_dma: + ti_csi2rx_cleanup_dma(csi); + return ret; +} + +static int ti_csi2rx_remove(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev); + + if (vb2_is_busy(&csi->vidq)) + return -EBUSY; + + video_unregister_device(&csi->vdev); + + ti_csi2rx_cleanup_vb2q(csi); + ti_csi2rx_cleanup_subdev(csi); + ti_csi2rx_cleanup_v4l2(csi); + ti_csi2rx_cleanup_dma(csi); + + return 0; +} + +static const struct of_device_id ti_csi2rx_of_match[] = { + { .compatible = "ti,j721e-csi2rx", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ti_csi2rx_of_match); + +static struct platform_driver ti_csi2rx_pdrv = { + .probe = ti_csi2rx_probe, + .remove = ti_csi2rx_remove, + .driver = { + .name = TI_CSI2RX_MODULE_NAME, + .of_match_table = ti_csi2rx_of_match, + }, +}; + +module_platform_driver(ti_csi2rx_pdrv); + +MODULE_DESCRIPTION("TI J721E CSI2 RX Driver"); +MODULE_AUTHOR("Pratyush Yadav "); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); From patchwork Wed May 26 15:23:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74618 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvP1-005CnZ-Iz; Wed, 26 May 2021 15:25:00 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235390AbhEZP02 (ORCPT + 1 other); Wed, 26 May 2021 11:26:28 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59440 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235541AbhEZP0T (ORCPT ); Wed, 26 May 2021 11:26:19 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOQtE001833; Wed, 26 May 2021 10:24:26 -0500 DKIM-Signature: v=1; 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Wed, 26 May 2021 10:24:26 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jm056314; Wed, 26 May 2021 10:24:22 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 14/18] media: dt-bindings: Add DT bindings for TI J721E CSI2RX driver Date: Wed, 26 May 2021 20:53:04 +0530 Message-ID: <20210526152308.16525-15-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav --- Changes in v2: - Rename to ti,j721e-csi2rx.yaml - Add an entry in MAINTAINERS. - Add a description for the binding. - Change compatible to ti,j721e-csi2rx to make it SoC specific. - Remove description from dmas, reg, power-domains. - Remove a limit of 2 from #address-cells and #size-cells. - Fix add ^ to csi-bridge subnode regex. - Make ranges mandatory. - Add unit address in example. - Add a reference to cdns,csi2rx in csi-bridge subnode. - Expand the example to include the csi-bridge subnode as well. - Re-order subject prefixes. .../bindings/media/ti,j721e-csi2rx.yaml | 101 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml new file mode 100644 index 000000000000..db87cfd65bed --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E CSI2RX Wrapper Device Tree Bindings + +description: | + The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that + enables sending captured frames to memory over PSI-L DMA. In the J721E + Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the + CSI_RX_IF section. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: ti,j721e-csi2rx + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ranges: true + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "^csi-bridge@": + type: object + description: CSI2 bridge node. + $ref: cdns,csi2rx.yaml# + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x4500000 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cdns_csi2rx: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x4504000 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + + reg = <0>; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2cf140a02063..1f9de488564d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18336,6 +18336,7 @@ TI J721E CSI2RX DRIVER M: Pratyush Yadav L: linux-media@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml F: drivers/media/platform/ti/j721e-csi2rx/ TI DAVINCI MACHINE SUPPORT From patchwork Wed May 26 15:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74621 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvP6-005CnZ-IR; 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Wed, 26 May 2021 10:24:32 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:31 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jn056314; Wed, 26 May 2021 10:24:27 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 15/18] media: dt-bindings: Convert Cadence CSI2RX binding to YAML Date: Wed, 26 May 2021 20:53:05 +0530 Message-ID: <20210526152308.16525-16-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Convert the Cadence CSI2RX binding to use YAML schema. Signed-off-by: Pratyush Yadav --- Changes in v2: - New in v2. .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------- .../bindings/media/cdns,csi2rx.yaml | 164 ++++++++++++++++++ 2 files changed, 164 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt deleted file mode 100644 index 6b02a0657ad9..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml new file mode 100644 index 000000000000..ff5dd4211ac9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence MIPI-CSI2 RX controller + +description: | + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI + lanes in input, and 4 different pixel streams in output. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,csi2rx + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 6 + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: sys_clk # main clock + - const: p_clk # register bank clock + - const: pixel_if0_clk # pixel stream 0 output clock + - const: pixel_if1_clk # pixel stream 1 output clock + - const: pixel_if2_clk # pixel stream 2 output clock + - const: pixel_if3_clk # pixel stream 3 output clock + + phys: + maxItems: 1 + description: phandle to the external D-PHY + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + maxItems: 1 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 0 output + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 1 output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 2 output + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 3 output + + required: + - port@0 + + +dependencies: + phys: [ 'phy-names' ] + phy-names: [ 'phys' ] + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + csi2rx: csi-bridge@d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; + }; From patchwork Wed May 26 15:23:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74622 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvPE-005Con-UI; Wed, 26 May 2021 15:25:13 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235444AbhEZP0k (ORCPT + 1 other); Wed, 26 May 2021 11:26:40 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59488 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235445AbhEZP0T (ORCPT ); Wed, 26 May 2021 11:26:19 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFObNA001908; Wed, 26 May 2021 10:24:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042677; bh=BM8CYX6t4azDDdhNFXFaitt4bQWfmarH8KCUYWOb5UE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m1ZD7I19PZQxRAYL5+PIJbo1XBR2hguCqOb4CygkI+JJ8FZlj/taJGw5TNiKu4z+M DC2wU9helezvyiYecMHcfUgmyxJmm1tQNgyUA5pDJuUM0hbGoicqNrUovG2kAXA/8T 6kgfAV+DsEM+ffPMmQfjQx+EQcr6X29e30upuGXE= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFObc2079558 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:37 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:36 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:36 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jo056314; Wed, 26 May 2021 10:24:32 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 16/18] phy: dt-bindings: Convert Cadence DPHY binding to YAML Date: Wed, 26 May 2021 20:53:06 +0530 Message-ID: <20210526152308.16525-17-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no Convert Cadence DPHY binding to YAML. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring --- Changes in v2: - Drop reg description. - Add a description for each DPHY clock. - Rename dphy@... to phy@... in example. - Add Laurent's R-by. - Re-order subject prefixes. .../devicetree/bindings/phy/cdns,dphy.txt | 20 -------- .../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted file mode 100644 index 1095bc4e72d9..000000000000 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt +++ /dev/null @@ -1,20 +0,0 @@ -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml new file mode 100644 index 000000000000..b90a58773bf2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Device Tree Bindings + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,dphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PMA state machine clock + - description: PLL reference clock + + clock-names: + items: + - const: psm + - const: pll_ref + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + dphy0: phy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0xfd0e0000 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; From patchwork Wed May 26 15:23:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74624 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvPI-005CpI-Uj; Wed, 26 May 2021 15:25:17 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234721AbhEZP0o (ORCPT + 1 other); Wed, 26 May 2021 11:26:44 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59500 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235527AbhEZP0U (ORCPT ); Wed, 26 May 2021 11:26:20 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOgLh001936; Wed, 26 May 2021 10:24:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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Wed, 26 May 2021 10:24:42 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jp056314; Wed, 26 May 2021 10:24:37 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 17/18] phy: dt-bindings: cdns,dphy: make clocks optional Date: Wed, 26 May 2021 20:53:07 +0530 Message-ID: <20210526152308.16525-18-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no The clocks are not used by the DPHY when used in Rx mode so make them optional. Signed-off-by: Pratyush Yadav Acked-by: Rob Herring --- Changes in v2: - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index b90a58773bf2..3bb5be05e825 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -33,8 +33,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - "#phy-cells" additionalProperties: false From patchwork Wed May 26 15:23:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 74625 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1llvPJ-005CpI-Sc; Wed, 26 May 2021 15:25:18 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235538AbhEZP0q (ORCPT + 1 other); Wed, 26 May 2021 11:26:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57454 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235494AbhEZP0Z (ORCPT ); Wed, 26 May 2021 11:26:25 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOl2g077230; Wed, 26 May 2021 10:24:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042687; bh=pTeLkA7bx6KOILpF/7/Br9MYMivB1gWNfgEKpM+42C8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Sa7mg3swfvYSY5fEXKTgFe09iCQMa2L+FTlEWUMbpwsMjpcWUDtgYtK6Dp/UXnW/P j+OpLrzDllzOFoSXaPXwT0uWNqSCdjOUuTLxmcYF6bTsY17Isw+Csql30A5SUx+b+Y VtuwpRJKGC6K7VbYpNkYlqb5SLO5QxQYfZ+gyv58= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFOlj0079626 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:47 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:47 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:47 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jq056314; Wed, 26 May 2021 10:24:42 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 18/18] phy: dt-bindings: cdns,dphy: add power-domains property Date: Wed, 26 May 2021 20:53:08 +0530 Message-ID: <20210526152308.16525-19-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -3.2 (---) X-LSpam-Report: No, score=-3.2 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_LOW=-0.7 autolearn=ham autolearn_force=no This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Acked-by: Rob Herring --- Changes in v2: - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index 3bb5be05e825..d5a5e1f0b671 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -39,11 +42,13 @@ additionalProperties: false examples: - | + #include dphy0: phy@fd0e0000{ compatible = "cdns,dphy"; reg = <0xfd0e0000 0x1000>; clocks = <&psm_clk>, <&pll_ref_clk>; clock-names = "psm", "pll_ref"; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; #phy-cells = <0>; };