From patchwork Thu Jul 23 23:50:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65801 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksu-00AkNh-Cq; Thu, 23 Jul 2020 23:44:20 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728595AbgGWXtY (ORCPT + 1 other); Thu, 23 Jul 2020 19:49:24 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:17987 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728196AbgGWXsR (ORCPT ); Thu, 23 Jul 2020 19:48:17 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:17 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:17 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:17 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 01/14] i2c: tegra: Don't mark VI I2C as IRQ safe runtime PM Date: Thu, 23 Jul 2020 16:50:59 -0700 Message-ID: <1595548272-9809-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548034; bh=zxB65TqmmcKmPfWkLJU50AtZToCBrCGEYlb/JsyjY+U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Fl8tqvlySxeFQDQY+54PsTN9/Ap3KRcNINo11fVdby3IDSAfwpkG/gnQHKKq0aUdJ z6/23I17/nIZNyD47iGPQM2JX2PaOUtGzNfJwDdHn1+QuQhAfthEeKt2cMqbzZnbQy yAp4FZCOpjj8XQiNb4AJOWXCUefYA2o0KVdgK1X3CkSQVO8lV8HO/0ynCtMV11Rjvg v5ad1aLajISWQCt8Hm8tLz5bgc4tuNSCIGbU4y5bcxtjcQPh4NCrq6MPDjC9tO4lVD 7Md3yFMMszQxoqAUB6JLrzGdUY4qKl8GRTvTwEZ2xSQC3GynxDEDAhn5r/03udxjTW vrvkdslNLO0Ag== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra VI I2C is part of VE power domain and typically used for camera usecases. VE power domain is not always on and is non-IRQ safe. So, IRQ safe device cannot be attached to a non-IRQ safe domain as it prevents powering off the PM domain and generic power domain driver will warn. Current driver marks all I2C devices as IRQ safe and VI I2C device does not require IRQ safe as it will not be used for atomic transfers. This patch has fix to make VI I2C as non-IRQ safe. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1577296..3be1018 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1750,7 +1750,15 @@ static int tegra_i2c_probe(struct platform_device *pdev) goto unprepare_slow_clk; } - pm_runtime_irq_safe(&pdev->dev); + /* + * VI I2C is in VE power domain which is not always on and not + * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ + * safe domain as it prevents powering off the PM domain. + * Also, VI I2C device don't need to use runtime IRQ safe as it will + * not be used for atomic transfers. + */ + if (!i2c_dev->is_vi) + pm_runtime_irq_safe(&pdev->dev); pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { ret = tegra_i2c_runtime_resume(&pdev->dev); From patchwork Thu Jul 23 23:51:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65788 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jykrx-00AkL4-Pn; Thu, 23 Jul 2020 23:43:22 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728390AbgGWXsV (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:21 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:7650 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728194AbgGWXsT (ORCPT ); Thu, 23 Jul 2020 19:48:19 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:48:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:18 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:18 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:17 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:17 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 02/14] i2c: tegra: Remove NULL pointer check before clk_enable/disable/prepare/unprepare Date: Thu, 23 Jul 2020 16:51:00 -0700 Message-ID: <1595548272-9809-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548085; bh=jD0igf8U1bTJzOqQcNuwvqEC25xsAMW3RMlh+sdfw58=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ENPrKbk31hDdtOdLpNXjzsNn+ZpaqkAbsmKyMQNFeyBEMePQLr53Fyi5MJzlLm2NK lTq7IZtJTAepkSsqXcTApOvJJBQEJv9zG/LdzmKh15/xQa5j9Tz5wurZWqzb3BhpXP qXY9xLxdmpT3xfr+B4r5pplHVlcvs9ygjRg7Yb2kJFxKdyI6LBsxV0OHvTuty+h2Z1 R6dEVhfW8FdGBKDtfmyHMnwgbdRjtZCisZghA/nAx0IwAmJjvCiUbGm2fQ7iPJ2op8 pRwyAIGVAQpOpmv0uFy8FzxxnFs40x+FCmSSH4EO6dVmcZ6wXk/bMg40qB0F66R4FD 3SITAuf3L120A== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no clk_enable, clk_disable, clk_prepare, and clk_unprepare APIs have implementation for checking clk pointer not NULL and clock consumers can safely call these APIs without NULL pointer check. So, this patch cleans up Tegra i2c driver to remove explicit checks before these APIs. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 64 +++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3be1018..c91307b9 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -655,21 +655,17 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) if (ret) return ret; - if (!i2c_dev->hw->has_single_clk_source) { - ret = clk_enable(i2c_dev->fast_clk); - if (ret < 0) { - dev_err(i2c_dev->dev, - "Enabling fast clk failed, err %d\n", ret); - return ret; - } + ret = clk_enable(i2c_dev->fast_clk); + if (ret < 0) { + dev_err(i2c_dev->dev, + "Enabling fast clk failed, err %d\n", ret); + return ret; } - if (i2c_dev->slow_clk) { - ret = clk_enable(i2c_dev->slow_clk); - if (ret < 0) { - dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; - } + ret = clk_enable(i2c_dev->slow_clk); + if (ret < 0) { + dev_err(dev, "failed to enable slow clock: %d\n", ret); + return ret; } ret = clk_enable(i2c_dev->div_clk); @@ -688,12 +684,8 @@ static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); clk_disable(i2c_dev->div_clk); - - if (i2c_dev->slow_clk) - clk_disable(i2c_dev->slow_clk); - - if (!i2c_dev->hw->has_single_clk_source) - clk_disable(i2c_dev->fast_clk); + clk_disable(i2c_dev->slow_clk); + clk_disable(i2c_dev->fast_clk); return pinctrl_pm_select_idle_state(i2c_dev->dev); } @@ -1716,20 +1708,16 @@ static int tegra_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, i2c_dev); - if (!i2c_dev->hw->has_single_clk_source) { - ret = clk_prepare(i2c_dev->fast_clk); - if (ret < 0) { - dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); - return ret; - } + ret = clk_prepare(i2c_dev->fast_clk); + if (ret < 0) { + dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); + return ret; } - if (i2c_dev->slow_clk) { - ret = clk_prepare(i2c_dev->slow_clk); - if (ret < 0) { - dev_err(dev, "failed to prepare slow clock: %d\n", ret); - goto unprepare_fast_clk; - } + ret = clk_prepare(i2c_dev->slow_clk); + if (ret < 0) { + dev_err(dev, "failed to prepare slow clock: %d\n", ret); + goto unprepare_fast_clk; } if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ && @@ -1843,12 +1831,10 @@ static int tegra_i2c_probe(struct platform_device *pdev) clk_unprepare(i2c_dev->div_clk); unprepare_slow_clk: - if (i2c_dev->is_vi) - clk_unprepare(i2c_dev->slow_clk); + clk_unprepare(i2c_dev->slow_clk); unprepare_fast_clk: - if (!i2c_dev->hw->has_single_clk_source) - clk_unprepare(i2c_dev->fast_clk); + clk_unprepare(i2c_dev->fast_clk); return ret; } @@ -1867,12 +1853,8 @@ static int tegra_i2c_remove(struct platform_device *pdev) tegra_i2c_runtime_suspend(&pdev->dev); clk_unprepare(i2c_dev->div_clk); - - if (i2c_dev->slow_clk) - clk_unprepare(i2c_dev->slow_clk); - - if (!i2c_dev->hw->has_single_clk_source) - clk_unprepare(i2c_dev->fast_clk); + clk_unprepare(i2c_dev->slow_clk); + clk_unprepare(i2c_dev->fast_clk); tegra_i2c_release_dma(i2c_dev); return 0; From patchwork Thu Jul 23 23:51:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65800 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksr-00AkNh-KR; Thu, 23 Jul 2020 23:44:18 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728375AbgGWXsU (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:20 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:17993 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728361AbgGWXsT (ORCPT ); Thu, 23 Jul 2020 19:48:19 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:18 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:18 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:18 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:18 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:18 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 03/14] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume Date: Thu, 23 Jul 2020 16:51:01 -0700 Message-ID: <1595548272-9809-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548035; bh=eufXsoZ14WkRUf36lqjK6lfwNSwXZDr32mhUx6fHlSE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=GyJ1vhtqJ3xldvtM5bdGL3aj2uZlCQL/Al5ZopfVFtN/2FE3WPwKkbLI+d8ENnV13 WCjP+iphCOu/3nY4rP1s2/H/c4t0CsJmj6+GoSRYAF07dHdSTBmlp6TLZYEPJ82yWq 9L3GRBEUhSE7cM8QcO9NG+jJns4cvSKTibQVjQ3FfQzdltOGV3makqy6ZnymOfINlO E4B7VYqvDvhRutOHqWuF1wyPBolyu83kBAdMjEm5DhxFRtFSm4DvOwj5GMS4rk/V7P s6vk/sLQ5pfdUpgiYpstsTvDafiZ+5RwAjQu6Mba1u94tltX9Eau6+ETs6ZTmTp6i2 vl7MHOzQjv0PA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no tegra_i2c_runtime_resume does not disable prior enabled clocks properly. This patch fixes it. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c91307b9..7b93c45 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -665,18 +665,23 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) ret = clk_enable(i2c_dev->slow_clk); if (ret < 0) { dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; + goto disable_fast_clk; } ret = clk_enable(i2c_dev->div_clk); if (ret < 0) { dev_err(i2c_dev->dev, "Enabling div clk failed, err %d\n", ret); - clk_disable(i2c_dev->fast_clk); - return ret; + goto disable_slow_clk; } return 0; + +disable_slow_clk: + clk_disable(i2c_dev->slow_clk); +disable_fast_clk: + clk_disable(i2c_dev->fast_clk); + return ret; } static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) From patchwork Thu Jul 23 23:51:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65789 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jykrz-00AkL4-4z; Thu, 23 Jul 2020 23:43:23 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728407AbgGWXsW (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:22 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:7661 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728364AbgGWXsT (ORCPT ); Thu, 23 Jul 2020 19:48:19 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:48:07 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:19 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Jul 2020 16:48:19 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:19 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:18 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 04/14] i2c: tegra: Fix runtime resume to re-init VI I2C Date: Thu, 23 Jul 2020 16:51:02 -0700 Message-ID: <1595548272-9809-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548087; bh=rVT7elWIzK6dQfAm9YaBBuoEEleair7GkfBCOrcVb5U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jKBpT3+3s55E2h9AArSUiywyocG4pjbOBhVwPfwkX1Mtqm90/N3w1vW/NaefYSIM2 EUHw+9EbnKSoHBy4GOXtYuYPbRfZWdSG+yfELAwEkuF1QCyjwG1VTEV8jD9Ikt6BQj YBHiIjAZCqNhzHoH7iBOn4Csp3PICSRkD6fzcWW4Ad7ap7zxPcVouD4CWLEQwkVZAn k7QEdrD9DkoX9xIZPn7uqvNU2QVcQQtzoFPVxN76B03UqAt/1y7jIf4cK1FzY1hhc2 xrXVjCaod9P22W29FUsUo42cfqWYGc/mRm/aCQt/AZrGmu0zpkqqfVwYAXliNiq4J8 oywWiv9A7VflA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus and is part of VE power domain. During suspend/resume VE power domain goes through power off/on. So, controller reset followed by i2c re-initialization is required after the domain power up. This patch fixes it. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 7b93c45..1bf3666 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -293,6 +293,8 @@ struct tegra_i2c_dev { bool is_curr_atomic_xfer; }; +static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit); + static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) { @@ -675,8 +677,22 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) goto disable_slow_clk; } + /* + * VI I2C device is attached to VE power domain which goes through + * power ON/OFF during PM runtime resume/suspend. So, controller + * should go through reset and need to re-initialize after power + * domain ON. + */ + if (i2c_dev->is_vi) { + ret = tegra_i2c_init(i2c_dev, true); + if (ret) + goto disable_div_clk; + } + return 0; +disable_div_clk: + clk_disable(i2c_dev->div_clk); disable_slow_clk: clk_disable(i2c_dev->slow_clk); disable_fast_clk: From patchwork Thu Jul 23 23:51:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65797 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksc-00AkMB-8C; Thu, 23 Jul 2020 23:44:02 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728411AbgGWXsW (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:22 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18000 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728365AbgGWXsU (ORCPT ); Thu, 23 Jul 2020 19:48:20 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:20 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:20 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:19 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:19 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 05/14] i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c Date: Thu, 23 Jul 2020 16:51:03 -0700 Message-ID: <1595548272-9809-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548037; bh=bx39F/3n9Q/pzD3y/Hu3Hjt/owO0zkylWWejNtiAobk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qVyF7SDPZZZmUHi235rXe9O3SBpwSgdM+Za095FHpwcJQb5kdD4vhuVbt8f9et0hZ NRiqqNfmIE5geiC187F/Wr8FDMxD95mqh7kBXBcavGfEAS7pYySawbTIfSnDGCHKB7 RnGZW9SgZ55M27oEbnphvPaSB0bY2eJhO7wdRkI74Xwium9/sjYEdJIX4LqvbN+jfF Apq53wBDOi2h9JXxHGRaQtw7jpvuHhqp4kWzTiWA7SyyCRUVav3xXo41JmAEui4Ews 8S3rjefI3uLDXcGOApOKqcLIG+WauTP3ySNFnehA0sZYvW9XaIeS51BTlly4wDyjv/ T/ng0NaZPAW5w== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus so APB DMA can't be used for Tegra210 VI I2C and there are no tx and rx dma channels for VI I2C. So, avoid attempt of requesting DMA channels. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1bf3666..00d3e4d 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -421,7 +421,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) dma_addr_t dma_phys; int err; - if (!i2c_dev->hw->has_apb_dma) + if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) return 0; if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { From patchwork Thu Jul 23 23:51:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65799 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksq-00AkNh-6J; Thu, 23 Jul 2020 23:44:16 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728578AbgGWXtQ (ORCPT + 1 other); Thu, 23 Jul 2020 19:49:16 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17654 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728380AbgGWXsV (ORCPT ); Thu, 23 Jul 2020 19:48:21 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:46:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:20 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Jul 2020 16:48:20 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:20 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:20 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:20 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 06/14] media: tegra-video: Fix channel format alignment Date: Thu, 23 Jul 2020 16:51:04 -0700 Message-ID: <1595548272-9809-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595547978; bh=8GJbUvoTqNXQhoilqMQO06MgCPv5IgO6eahUeR7/0ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=I1Togn/1+hQHpUowTkWtC76GKzlKM4rbMYAjd9SBrfknD3w4xue2ptmitNKwQFPmt DEB7jl2eTArWMU4ph15iZleVqC9rGaFIEIjya2ZYUKL4zhgv0ghxFz3VC9x2w6bFVL 4H1AQF0JF/iSySsDfvrObAbkn+TQfMr6yRntCTIb0q4i8YGW9SZI7q62FmIWyI3McK cZCWvXRJZSUGpma8iEP/o8uLR6x5V5jjTeo/OByqMYHDBoE9aU+xHIt/s+kEw+LVzH mK7rphMRUWEaZXQWpgTz1SqwIOMI0K6pFFg4DcTPRk/nyuxsVmsRLvyTt5bhHioeKt kbXgEVtb8AooQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 1b5e660..d621ebc 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per From patchwork Thu Jul 23 23:51:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65795 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksU-00AkMB-Oz; Thu, 23 Jul 2020 23:43:55 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728543AbgGWXs6 (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:58 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:7670 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728392AbgGWXsW (ORCPT ); Thu, 23 Jul 2020 19:48:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:48:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:21 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:20 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:20 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 07/14] media: tegra-video: Enable TPG based on kernel config Date: Thu, 23 Jul 2020 16:51:05 -0700 Message-ID: <1595548272-9809-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548088; bh=ds7oxXGxAuyDw53E4hJLEBinWlNAsgh9dJ6sWX9tefI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=anKqe2mrelehIEqA1YnoIEAMG9KHvjFSlOLXGCO6GpAS6GMLrxZQ3VqANa1UWUaVK oOPZrcAKRuJpOV0dS5c5SulL3Pt/VenZFqct3Mnu0kO5SZvrw4qJmARFr9vNzBmxee wJgcZZlZ5FUNqlebYADarKY2Vnk63s8hTbhgHD/6mzCNMJqftinwU0syimbbR6Po+i 3Pu2pzLD6qOVTBUnOCpesAtSXlk3r0t+GIruNQjaPrqPIoSKBhbxSEzKv4wcZEJ22W DF+co2DH4DWNNsOMwxjuqlS/fpDIJuYCgnmGf2kJrCqh/hyJ8Dp+9kQPctIT6N7uKZ aKCX+glSd03Vw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra internal TPG mode is only for Tegra vi and csi testing without a real sensor and driver should default support real sensor. So, This patch adds CONFIG_VIDEO_TEGRA_TPG and enables Tegra internal TPG mode only when this config is selected. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 6 +++++ drivers/staging/media/tegra-video/csi.c | 38 +++++++++++++++++++++++----- drivers/staging/media/tegra-video/tegra210.c | 6 +++++ drivers/staging/media/tegra-video/vi.c | 13 +++++++--- drivers/staging/media/tegra-video/video.c | 23 +++++++++-------- 5 files changed, 65 insertions(+), 21 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index f6c61ec..566da62 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -10,3 +10,9 @@ config VIDEO_TEGRA To compile this driver as a module, choose M here: the module will be called tegra-video. + +config VIDEO_TEGRA_TPG + bool "NVIDIA Tegra VI driver TPG mode" + depends on VIDEO_TEGRA + help + Say yes here to enable Tegra internal TPG mode diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 40ea195..fb667df 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -62,6 +62,9 @@ static int csi_enum_bus_code(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_mbus_code_enum *code) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) return -EINVAL; @@ -76,6 +79,9 @@ static int csi_get_format(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + fmt->format = csi_chan->format; return 0; @@ -121,6 +127,9 @@ static int csi_enum_framesizes(struct v4l2_subdev *subdev, { unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) return -EINVAL; @@ -148,6 +157,9 @@ static int csi_enum_frameintervals(struct v4l2_subdev *subdev, const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; int index; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + /* one framerate per format and resolution */ if (fie->index > 0) return -EINVAL; @@ -172,6 +184,9 @@ static int csi_set_format(struct v4l2_subdev *subdev, const struct v4l2_frmsize_discrete *sizes; unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, ARRAY_SIZE(tegra_csi_tpg_sizes), width, height, @@ -208,6 +223,9 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + vfi->interval.numerator = 1; vfi->interval.denominator = csi_chan->framerate; @@ -311,8 +329,12 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) subdev = &chan->subdev; v4l2_subdev_init(subdev, &tegra_csi_ops); subdev->dev = csi->dev; - snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", - chan->csi_port_num); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", + chan->csi_port_num); + else + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", + kbasename(chan->of_node->full_name)); v4l2_set_subdevdata(subdev, chan); subdev->fwnode = of_fwnode_handle(chan->of_node); @@ -405,11 +427,13 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_csi_tpg_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto cleanup; + } } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3baa4e3..3492a8a 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -631,7 +631,11 @@ const struct tegra_vi_soc tegra210_vi_soc = { .ops = &tegra210_vi_ops, .hw_revision = 3, .vi_max_channels = 6, +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) .vi_max_clk_hz = 499200000, +#else + .vi_max_clk_hz = 998400000, +#endif }; /* Tegra210 CSI PHY registers accessors */ @@ -957,7 +961,9 @@ static const char * const tegra210_csi_cil_clks[] = { "cilab", "cilcd", "cile", +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) "csi_tpg", +#endif }; /* Tegra210 CSI operations */ diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index d621ebc..0197f4e 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -565,6 +565,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) { int ret; +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) /* add test pattern control handler to v4l2 device */ v4l2_ctrl_new_std_menu_items(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_TEST_PATTERN, @@ -576,6 +577,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#endif /* setup the controls */ ret = v4l2_ctrl_handler_setup(&chan->ctrl_handler); @@ -918,10 +920,13 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, "failed to allocate tpg channels: %d\n", ret); - goto free_chans; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_tpg_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto free_chans; + } } ret = tegra_vi_channels_init(vi); diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/media/tegra-video/video.c index 30816aa..e50bd70 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -60,15 +60,17 @@ static int host1x_video_probe(struct host1x_device *dev) if (ret < 0) goto unregister_v4l2; - /* - * Both vi and csi channels are available now. - * Register v4l2 nodes and create media links for TPG. - */ - ret = tegra_v4l2_nodes_setup_tpg(vid); - if (ret < 0) { - dev_err(&dev->dev, - "failed to setup tpg graph: %d\n", ret); - goto device_exit; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + /* + * Both vi and csi channels are available now. + * Register v4l2 nodes and create media links for TPG. + */ + ret = tegra_v4l2_nodes_setup_tpg(vid); + if (ret < 0) { + dev_err(&dev->dev, + "failed to setup tpg graph: %d\n", ret); + goto device_exit; + } } return 0; @@ -91,7 +93,8 @@ static int host1x_video_remove(struct host1x_device *dev) { struct tegra_video_device *vid = dev_get_drvdata(&dev->dev); - tegra_v4l2_nodes_cleanup_tpg(vid); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_v4l2_nodes_cleanup_tpg(vid); host1x_device_exit(dev); From patchwork Thu Jul 23 23:51:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65798 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksi-00AkNK-3M; Thu, 23 Jul 2020 23:44:08 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728562AbgGWXtI (ORCPT + 1 other); Thu, 23 Jul 2020 19:49:08 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18010 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728403AbgGWXsW (ORCPT ); Thu, 23 Jul 2020 19:48:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:21 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:21 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:21 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 08/14] media: tegra-video: Update format lookup to offset based Date: Thu, 23 Jul 2020 16:51:06 -0700 Message-ID: <1595548272-9809-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; 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This patch updates the helper function for format lookup based on mbus code from pre-defined Tegra supported format list to look from the specified list index offset. Offset based look up is used with sensor device graph (non TPG) where format enumeration can list all supported formats for the specific sensor mbus codes. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 0197f4e..52d751f 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -53,11 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) } static int tegra_get_format_idx_by_code(struct tegra_vi *vi, - unsigned int code) + unsigned int code, + unsigned int offset) { unsigned int i; - for (i = 0; i < vi->soc->nformats; ++i) { + for (i = offset; i < vi->soc->nformats; ++i) { if (vi->soc->video_formats[i].code == code) return i; } @@ -598,11 +599,12 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_zero(chan->tpg_fmts_bitmap, MAX_FORMAT_NUM); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_SRGGB10_1X10); + MEDIA_BUS_FMT_SRGGB10_1X10, 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_RGB888_1X32_PADHI); + MEDIA_BUS_FMT_RGB888_1X32_PADHI, + 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); } From patchwork Thu Jul 23 23:51:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65796 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksa-00AkMB-4M; Thu, 23 Jul 2020 23:44:00 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728533AbgGWXs5 (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:57 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17662 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728414AbgGWXsX (ORCPT ); Thu, 23 Jul 2020 19:48:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:46:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:22 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:22 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:22 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 09/14] dt-bindings: tegra: Update VI and CSI bindings with port info Date: Thu, 23 Jul 2020 16:51:07 -0700 Message-ID: <1595548272-9809-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595547980; bh=BnlKr3cpHbqR2/ypGaWrf+nRHayXIJrs4Q9+28+PHhQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fkj8yCjtuA2reQ68Lrmn/0js88LviK2hKfOg4fhzvbRhUdKMKR+Ig1F/TCobNSYTY rO4Z/Twi4FnLxQiO0BxDFhIhv1U9R2x9QRg4Pt4xUc/88vhbsWKqi7y2iKuybanX6r pgzc3VCBmIH32K8SaIAs6VbDNc/w8OGXcWchkW6/o7H/W6+36bP//fCFFGqdYlu8kp OUb93gr30zWhrnHn+5LpllnvEIBDTcEcxMHCfvvubq3y6csKiQZR6m/VkYYGVyv/UZ OtTlY2EzFg0K9vU9DbReRMnfx5+Gk2FPrixda4l6et29UYicmW3T50/4wDfeNXGxgb 0uC5HYkL2pbuQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Update VI and CSI bindings to add port and endpoint nodes as per media video-interfaces DT binding document. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 92 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 4731921..ac63ae4a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -51,8 +51,16 @@ of the following host1x client modules: - vi - Tegra210: - power-domains: Must include venc powergate node as vi is in VE partition. - - Tegra210 has CSI part of VI sharing same host interface and register space. - So, VI device node should have CSI child node. + + ports (optional node) + vi can have optional ports node and max 6 ports are supported. Each port + should have single 'endpoint' child node. All port nodes are grouped under + ports node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + csi (required node) + Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. - csi: mipi csi interface to vi @@ -65,6 +73,46 @@ of the following host1x client modules: - power-domains: Must include sor powergate node as csicil is in SOR partition. + channel (optional nodes) + Maximum 6 channels are supported with each csi brick as either x4 or x2 + based on hw connectivity to sensor. + + Required properties: + - reg: csi port number. Valid port numbers are 0 through 5. + - nvidia,mipi-calibrate: Should contain a phandle and a specifier + specifying which pads are used by this CSI port and need to be + calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. + + Each channel node must contain 2 port nodes which can be grouped + under 'ports' node and each port should have a single child 'endpoint' + node. + + ports node + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + ports node must contain below 2 port nodes. + port@0 with single child 'endpoint' node always a sink. + port@1 with single child 'endpoint' node always a source. + + port@0 (required node) + Required properties: + - reg: 0 + + endpoint (required node) + Required properties: + - data-lanes: an array of data lane from 1 to 4. Valid array + lengths are 1/2/4. + - remote-endpoint: phandle to sensor 'endpoint' node. + + port@1 (required node) + Required properties: + - reg: 1 + + endpoint (required node) + Required properties: + - remote-endpoint: phandle to vi port 'endpoint' node. + - epp: encoder pre-processor Required properties: @@ -340,6 +388,18 @@ Example: ranges = <0x0 0x0 0x54080000 0x2000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_vi_in0: endpoint { + remote-endpoint = <&imx219_csi_out0>; + }; + }; + }; + csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; @@ -362,6 +422,34 @@ Example: <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + nvidia,mipi-calibrate = <&mipi 0x001>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_csi_in0: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&imx219_out0>; + }; + }; + + port@1 { + reg = <1>; + imx219_csi_out0: endpoint { + remote-endpoint = <&imx219_vi_in0>; + }; + }; + }; + }; }; }; From patchwork Thu Jul 23 23:51:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65790 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyks0-00AkL4-6O; Thu, 23 Jul 2020 23:43:26 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728437AbgGWXsZ (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:25 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18015 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728418AbgGWXsY (ORCPT ); Thu, 23 Jul 2020 19:48:24 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:23 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Jul 2020 16:48:23 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:22 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:22 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 10/14] media: tegra-video: Add support for external sensor capture Date: Thu, 23 Jul 2020 16:51:08 -0700 Message-ID: <1595548272-9809-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548040; bh=m+1X/e0javVgfUC5VHu2bR78ONKFjyWaw/jt6xmF4Y4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=LISoZDWNuQV97Ke1lQlwmh8wKKpo9alid3nyaxhSg/zgN51LI4IbEkmSMxNr33KR0 uqeNie19vcT9VqMj+UnEEyFJATPq66iaZF1so497zZUDZo6tMw0eLFFmBNbn8HpufW 8SPGq9A77Gl010PEwl5SZUluHUnShnOgJLQ8dpqvSGPwbj1Lgdx8+2EiWSVZa4/ZHJ uPU4Y/hx+qfbJR3S7/7KlBOvT+o8epj9f6eRWxW/dEKqIF80Q1+3vNgiQV/Op3XJa9 Byxo1pzGyklxcC+BlAx9eBr87auTGD3ZDnEGAEzLcnw1G9Em8Ro2XluHmplSJlwqZH nsZ+RrnHILvcQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds support to capture from the external sensor based on device graph in the device tree. Driver walks through the device graph to create media links between the entities and registers and unregisters video devices when the corresponding sub-devices are bound and unbound. Channel formats are enumerated based on available formats from the sensor and the corresponding matched formats from the Tegra supported video formats list. Each Tegra CSI instance can be configured as 4-lane or 2-lane based on supported lane configuration from the sensor through the device tree. Currently this driver supports V4L2 video node centric only. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 1 + drivers/staging/media/tegra-video/csi.c | 130 +++++- drivers/staging/media/tegra-video/csi.h | 1 + drivers/staging/media/tegra-video/tegra210.c | 2 +- drivers/staging/media/tegra-video/vi.c | 648 +++++++++++++++++++++++++-- drivers/staging/media/tegra-video/vi.h | 25 +- 6 files changed, 749 insertions(+), 58 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index 566da62..1f35da4 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -5,6 +5,7 @@ config VIDEO_TEGRA depends on VIDEO_V4L2 select MEDIA_CONTROLLER select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE help Choose this option if you have an NVIDIA Tegra SoC. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index fb667df..c21dd09 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -9,10 +9,13 @@ #include #include #include +#include #include #include #include +#include + #include "csi.h" #include "video.h" @@ -285,26 +288,101 @@ static const struct v4l2_subdev_ops tegra_csi_ops = { .pad = &tegra_csi_pad_ops, }; +static int tegra_csi_channel_alloc(struct tegra_csi *csi, + struct device_node *node, + unsigned int port_num, unsigned int lanes, + unsigned int num_pads) +{ + struct tegra_csi_channel *chan; + + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + list_add_tail(&chan->list, &csi->csi_chans); + chan->csi = csi; + chan->csi_port_num = port_num; + chan->numlanes = lanes; + chan->of_node = node; + chan->numpads = num_pads; + if (num_pads & 0x2) { + chan->pads[0].flags = MEDIA_PAD_FL_SINK; + chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; + } else { + chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + } + + return 0; +} + static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) { struct device_node *node = csi->dev->of_node; unsigned int port_num; - struct tegra_csi_channel *chan; unsigned int tpg_channels = csi->soc->csi_max_channels; + int ret; /* allocate CSI channel for each CSI x2 ports */ for (port_num = 0; port_num < tpg_channels; port_num++) { - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; - - list_add_tail(&chan->list, &csi->csi_chans); - chan->csi = csi; - chan->csi_port_num = port_num; - chan->numlanes = 2; - chan->of_node = node; - chan->numpads = 1; - chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_csi_channels_alloc(struct tegra_csi *csi) +{ + struct device_node *node = csi->dev->of_node; + struct v4l2_fwnode_endpoint v4l2_ep = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + struct fwnode_handle *fwh; + struct device_node *channel; + struct device_node *ep; + unsigned int lanes, portno, num_pads; + int ret; + + for_each_child_of_node(node, channel) { + if (!of_node_name_eq(channel, "channel")) + continue; + + ret = of_property_read_u32(channel, "reg", &portno); + if (ret < 0) + continue; + + if (portno >= csi->soc->csi_max_channels) { + dev_err(csi->dev, "invalid port num %d\n", portno); + return -EINVAL; + } + + ep = of_graph_get_endpoint_by_regs(channel, 0, 0); + if (!ep) + continue; + + fwh = of_fwnode_handle(ep); + ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); + of_node_put(ep); + if (ret) { + dev_err(csi->dev, + "failed to parse v4l2 endpoint: %d\n", ret); + return ret; + } + + lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; + if (!lanes || ((lanes & (lanes - 1)) != 0)) { + dev_err(csi->dev, "invalid data-lanes %d\n", lanes); + return -EINVAL; + } + + num_pads = of_graph_get_endpoint_count(channel); + if (num_pads == TEGRA_CSI_PADS_NUM) { + ret = tegra_csi_channel_alloc(csi, channel, portno, + lanes, num_pads); + if (ret < 0) + return ret; + } } return 0; @@ -350,6 +428,15 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) return ret; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = v4l2_async_register_subdev(subdev); + if (ret < 0) { + dev_err(csi->dev, + "failed to register subdev: %d\n", ret); + return ret; + } + } + return 0; } @@ -389,8 +476,12 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { subdev = &chan->subdev; - if (subdev->dev) + if (subdev->dev) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_unregister_subdev(subdev); media_entity_cleanup(&subdev->entity); + } + list_del(&chan->list); kfree(chan); } @@ -427,13 +518,14 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; - } + else + ret = tegra_csi_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate channels: %d\n", ret); + goto cleanup; } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 93bd2a0..78a5110 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -7,6 +7,7 @@ #define __TEGRA_CSI_H__ #include +#include #include /* diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3492a8a..253bf33 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -230,7 +230,7 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) tegra_channel_capture_setup(chan); /* recover CSI block */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_csi_subdev(chan); tegra_csi_error_recover(subdev); } diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 52d751f..f7dbea2 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) return container_of(vb, struct tegra_channel_buffer, buf); } +static inline struct tegra_vi_graph_entity * +to_tegra_vi_graph_entity(struct v4l2_async_subdev *asd) +{ + return container_of(asd, struct tegra_vi_graph_entity, asd); +} + static int tegra_get_format_idx_by_code(struct tegra_vi *vi, unsigned int code, unsigned int offset) @@ -146,28 +153,64 @@ static void tegra_channel_buffer_queue(struct vb2_buffer *vb) } struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) +tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan) +{ + struct media_pad *pad; + + pad = media_entity_remote_pad(&chan->pad); + if (!pad) + return NULL; + + return media_entity_to_v4l2_subdev(pad->entity); +} + +struct v4l2_subdev * +tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan) { struct media_pad *pad; struct v4l2_subdev *subdev; struct media_entity *entity; - pad = media_entity_remote_pad(&chan->pad); - entity = pad->entity; - subdev = media_entity_to_v4l2_subdev(entity); + subdev = tegra_channel_get_remote_csi_subdev(chan); + if (!subdev) + return NULL; + + pad = &subdev->entity.pads[0]; + while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) { + pad = media_entity_remote_pad(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + entity = pad->entity; + pad = &entity->pads[0]; + subdev = media_entity_to_v4l2_subdev(entity); + } return subdev; } int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { - struct v4l2_subdev *subdev; + struct v4l2_subdev *subdev, *csi_subdev, *src_subdev; int ret; - /* stream CSI */ - subdev = tegra_channel_get_remote_subdev(chan); + csi_subdev = tegra_channel_get_remote_csi_subdev(chan); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + /* + * Tegra CSI receiver can detect the first LP to HS transition. + * So, start the CSI stream-on prior to sensor stream-on and + * vice-versa for stream-off. + */ + subdev = on ? csi_subdev : src_subdev; ret = v4l2_subdev_call(subdev, video, s_stream, on); - if (on && ret < 0 && ret != -ENOIOCTLCMD) + if (ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + subdev = on ? src_subdev : csi_subdev; + ret = v4l2_subdev_call(subdev, video, s_stream, on); + if (ret < 0 && ret != -ENOIOCTLCMD) return ret; return 0; @@ -252,7 +295,7 @@ static int tegra_channel_g_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); return v4l2_g_parm_cap(&chan->video, subdev, a); } @@ -262,7 +305,7 @@ static int tegra_channel_s_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); return v4l2_s_parm_cap(&chan->video, subdev, a); } @@ -284,7 +327,7 @@ static int tegra_channel_enum_framesizes(struct file *file, void *fh, fse.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); ret = v4l2_subdev_call(subdev, pad, enum_frame_size, NULL, &fse); if (ret) return ret; @@ -316,7 +359,7 @@ static int tegra_channel_enum_frameintervals(struct file *file, void *fh, fie.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); ret = v4l2_subdev_call(subdev, pad, enum_frame_interval, NULL, &fie); if (ret) return ret; @@ -335,6 +378,9 @@ static int tegra_channel_enum_format(struct file *file, void *fh, unsigned int index = 0, i; unsigned long *fmts_bitmap = chan->tpg_fmts_bitmap; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + fmts_bitmap = chan->fmts_bitmap; + if (f->index >= bitmap_weight(fmts_bitmap, MAX_FORMAT_NUM)) return -EINVAL; @@ -391,8 +437,12 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + int ret; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!subdev) + return -ENODEV; - subdev = tegra_channel_get_remote_subdev(chan); pad_cfg = v4l2_subdev_alloc_pad_config(subdev); if (!pad_cfg) return -ENOMEM; @@ -412,7 +462,10 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -452,8 +505,11 @@ static int tegra_channel_set_format(struct file *file, void *fh, fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - subdev = tegra_channel_get_remote_subdev(chan); - v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + subdev = tegra_channel_get_remote_source_subdev(chan); + ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -463,15 +519,50 @@ static int tegra_channel_set_format(struct file *file, void *fh, return 0; } +static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) +{ + int ret, index; + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + /* + * Initialize channel format to the sub-device active format if there + * is corresponding match in the Tegra supported video formats. + */ + subdev = tegra_channel_get_remote_source_subdev(chan); + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret) + return ret; + + index = tegra_get_format_idx_by_code(chan->vi, fmt.format.code, 0); + if (index < 0) + return -EINVAL; + + chan->fmtinfo = &chan->vi->soc->video_formats[index]; + v4l2_fill_pix_format(&chan->format, &fmt.format); + chan->format.pixelformat = chan->fmtinfo->fourcc; + chan->format.bytesperline = chan->format.width * chan->fmtinfo->bpp; + chan->format.sizeimage = chan->format.bytesperline * + chan->format.height; + tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + + return 0; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { - /* currently driver supports internal TPG only */ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + if (inp->index) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; - strscpy(inp->name, "Tegra TPG", sizeof(inp->name)); + subdev = tegra_channel_get_remote_source_subdev(chan); + strscpy(inp->name, subdev->name, sizeof(inp->name)); return 0; } @@ -578,6 +669,22 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#else + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!subdev) + return -ENODEV; + + ret = v4l2_ctrl_add_handler(&chan->ctrl_handler, subdev->ctrl_handler, + NULL, true); + if (ret < 0) { + dev_err(chan->vi->dev, + "failed to add subdev %s ctrl handler: %d\n", + subdev->name, ret); + v4l2_ctrl_handler_free(&chan->ctrl_handler); + return ret; + } #endif /* setup the controls */ @@ -608,6 +715,61 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_set(chan->tpg_fmts_bitmap, index, 1); } +static int vi_fmts_bitmap_init(struct tegra_vi_channel *chan) +{ + int index, ret, match_code = 0; + struct v4l2_subdev *subdev; + struct v4l2_subdev_mbus_code_enum code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM); + + /* + * Set the bitmap bits based on all the matched formats between the + * available media bus formats of sub-device and the pre-defined Tegra + * supported video formats. + */ + subdev = tegra_channel_get_remote_source_subdev(chan); + while (1) { + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code, + NULL, &code); + if (ret < 0) + break; + + index = tegra_get_format_idx_by_code(chan->vi, code.code, 0); + while (index >= 0) { + bitmap_set(chan->fmts_bitmap, index, 1); + if (!match_code) + match_code = code.code; + /* look for other formats with same mbus code */ + index = tegra_get_format_idx_by_code(chan->vi, + code.code, + index + 1); + } + + code.index++; + } + + /* + * Set the bitmap bit corresponding to default tegra video format if + * there are no matched formats. + */ + if (!match_code) { + match_code = tegra_default_format.code; + index = tegra_get_format_idx_by_code(chan->vi, match_code, 0); + if (WARN_ON(index < 0)) + return -EINVAL; + + bitmap_set(chan->fmts_bitmap, index, 1); + } + + /* initialize channel format to the sub-device active format */ + tegra_channel_set_subdev_active_fmt(chan); + + return 0; +} + static void tegra_channel_cleanup(struct tegra_vi_channel *chan) { v4l2_ctrl_handler_free(&chan->ctrl_handler); @@ -720,6 +882,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) goto free_v4l2_ctrl_hdl; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_notifier_init(&chan->notifier); + return 0; free_v4l2_ctrl_hdl: @@ -733,28 +898,84 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) return ret; } -static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, + struct device_node *node) { struct tegra_vi_channel *chan; + + /* + * Do not use devm_kzalloc as memory is freed immediately + * when device instance is unbound but application might still + * be holding the device node open. Channel memory allocated + * with kzalloc is freed during video device release callback. + */ + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->vi = vi; + chan->portno = port_num; + chan->of_node = node; + list_add_tail(&chan->list, &vi->vi_chans); + + return 0; +} + +static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +{ unsigned int port_num; unsigned int nchannels = vi->soc->vi_max_channels; + int ret; for (port_num = 0; port_num < nchannels; port_num++) { - /* - * Do not use devm_kzalloc as memory is freed immediately - * when device instance is unbound but application might still - * be holding the device node open. Channel memory allocated - * with kzalloc is freed during video device release callback. - */ - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; + ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_vi_channels_alloc(struct tegra_vi *vi) +{ + struct device_node *node = vi->dev->of_node; + struct device_node *ep = NULL; + struct device_node *ports; + struct device_node *port; + unsigned int port_num; + int ret; + + ports = of_get_child_by_name(node, "ports"); + if (!ports) + return -ENODEV; + + for_each_child_of_node(ports, port) { + if (!of_node_name_eq(port, "port")) + continue; + + ret = of_property_read_u32(port, "reg", &port_num); + if (ret < 0) + continue; + + if (port_num > vi->soc->vi_max_channels) { + of_node_put(ports); + dev_err(vi->dev, "invalid port num %d\n", port_num); + return -EINVAL; + } - chan->vi = vi; - chan->portno = port_num; - list_add_tail(&chan->list, &vi->vi_chans); + ep = of_get_child_by_name(port, "endpoint"); + if (!ep) + continue; + + of_node_put(ep); + ret = tegra_vi_channel_alloc(vi, port_num, port); + if (ret < 0) { + of_node_put(ports); + return ret; + } } + of_node_put(ports); return 0; } @@ -909,6 +1130,347 @@ static int __maybe_unused vi_runtime_suspend(struct device *dev) return 0; } +/* + * Graph Management + */ +static struct tegra_vi_graph_entity * +tegra_vi_graph_find_entity(struct tegra_vi_channel *chan, + const struct fwnode_handle *fwnode) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + if (entity->asd.match.fwnode == fwnode) + return entity; + } + + return NULL; +} + +static int tegra_vi_graph_build(struct tegra_vi_channel *chan, + struct tegra_vi_graph_entity *entity) +{ + struct tegra_vi *vi = chan->vi; + struct tegra_vi_graph_entity *ent; + struct fwnode_handle *ep = NULL; + struct v4l2_fwnode_link link; + struct media_entity *local = entity->entity; + struct media_entity *remote; + struct media_pad *local_pad; + struct media_pad *remote_pad; + u32 link_flags = MEDIA_LNK_FL_ENABLED; + int ret = 0; + + dev_dbg(vi->dev, "creating links for entity %s\n", local->name); + + while (1) { + ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode, + ep); + if (!ep) + break; + + ret = v4l2_fwnode_parse_link(ep, &link); + if (ret < 0) { + dev_err(vi->dev, "failed to parse link for %pOF: %d\n", + to_of_node(ep), ret); + continue; + } + + if (link.local_port >= local->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.local_port, to_of_node(link.local_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + local_pad = &local->pads[link.local_port]; + /* Remote node is vi node. So use channel video entity and pad + * as remote/sink. + */ + if (link.remote_node == of_fwnode_handle(vi->dev->of_node)) { + remote = &chan->video.entity; + remote_pad = &chan->pad; + goto create_link; + } + + /* + * Skip sink ports, they will be processed from the other end + * of the link. + */ + if (local_pad->flags & MEDIA_PAD_FL_SINK) { + dev_dbg(vi->dev, "skipping sink port %pOF:%u\n", + to_of_node(link.local_node), link.local_port); + v4l2_fwnode_put_link(&link); + continue; + } + + /* find the remote entity from notifier list */ + ent = tegra_vi_graph_find_entity(chan, link.remote_node); + if (!ent) { + dev_err(vi->dev, "no entity found for %pOF\n", + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -ENODEV; + break; + } + + remote = ent->entity; + if (link.remote_port >= remote->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.remote_port, + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + remote_pad = &remote->pads[link.remote_port]; + +create_link: + dev_dbg(vi->dev, "creating %s:%u -> %s:%u link\n", + local->name, local_pad->index, + remote->name, remote_pad->index); + + ret = media_create_pad_link(local, local_pad->index, + remote, remote_pad->index, + link_flags); + v4l2_fwnode_put_link(&link); + if (ret < 0) { + dev_err(vi->dev, + "failed to create %s:%u -> %s:%u link: %d\n", + local->name, local_pad->index, + remote->name, remote_pad->index, ret); + break; + } + } + + fwnode_handle_put(ep); + return ret; +} + +static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + struct v4l2_subdev *subdev; + struct tegra_vi_channel *chan; + struct tegra_vi *vi; + int ret; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + dev_dbg(vi->dev, "notify complete, all subdevs registered\n"); + + /* + * Video device node should be created at the end of all the device + * related initialization/setup. + * Current video_register_device() does both initialize and register + * video device in same API. + * + * TODO: Update v4l2-dev driver to split initialize and register into + * separate APIs and then update Tegra video driver to do video device + * initialize followed by all video device related setup and then + * register the video device. + */ + ret = video_register_device(&chan->video, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + dev_err(vi->dev, + "failed to register video device: %d\n", ret); + goto unregister_video; + } + + /* create links between the entities */ + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + ret = tegra_vi_graph_build(chan, entity); + if (ret < 0) + goto unregister_video; + } + + ret = tegra_channel_setup_ctrl_handler(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to setup channel controls: %d\n", ret); + goto unregister_video; + } + + ret = vi_fmts_bitmap_init(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to initialize formats bitmap: %d\n", ret); + goto unregister_video; + } + + subdev = tegra_channel_get_remote_csi_subdev(chan); + if (!subdev) { + ret = -ENODEV; + dev_err(vi->dev, + "failed to get remote csi subdev: %d\n", ret); + goto unregister_video; + } + + v4l2_set_subdev_hostdata(subdev, chan); + + return 0; + +unregister_video: + video_unregister_device(&chan->video); + return ret; +} + +static int tegra_vi_graph_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + /* + * Locate the entity corresponding to the bound subdev and store the + * subdev pointer. + */ + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (!entity) { + dev_err(vi->dev, "no entity for subdev %s\n", subdev->name); + return -EINVAL; + } + + if (entity->subdev) { + dev_err(vi->dev, "duplicate subdev for node %pOF\n", + to_of_node(entity->asd.match.fwnode)); + return -EINVAL; + } + + dev_dbg(vi->dev, "subdev %s bound\n", subdev->name); + entity->entity = &subdev->entity; + entity->subdev = subdev; + + return 0; +} + +static const struct v4l2_async_notifier_operations tegra_vi_async_ops = { + .bound = tegra_vi_graph_notify_bound, + .complete = tegra_vi_graph_notify_complete, +}; + +static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, + struct fwnode_handle *fwnode) +{ + struct tegra_vi *vi = chan->vi; + struct fwnode_handle *ep = NULL; + struct fwnode_handle *remote = NULL; + struct v4l2_async_subdev *asd; + struct device_node *node = NULL; + int ret; + + dev_dbg(vi->dev, "parsing node %pOF\n", to_of_node(fwnode)); + + /* parse all the remote entities and put them into the list */ + for_each_endpoint_of_node(to_of_node(fwnode), node) { + ep = of_fwnode_handle(node); + remote = fwnode_graph_get_remote_port_parent(ep); + if (!remote) { + dev_err(vi->dev, + "remote device at %pOF not found\n", node); + ret = -EINVAL; + goto cleanup; + } + + /* skip entities that are already processed */ + if (remote == dev_fwnode(vi->dev) || + tegra_vi_graph_find_entity(chan, remote)) { + fwnode_handle_put(remote); + continue; + } + + asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, + remote, sizeof(struct tegra_vi_graph_entity)); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + dev_err(vi->dev, + "failed to add subdev to notifier: %d\n", ret); + fwnode_handle_put(remote); + goto cleanup; + } + + ret = tegra_vi_graph_parse_one(chan, remote); + if (ret < 0) { + fwnode_handle_put(remote); + goto cleanup; + } + + fwnode_handle_put(remote); + } + + return 0; + +cleanup: + dev_err(vi->dev, "failed parsing the graph: %d\n", ret); + v4l2_async_notifier_cleanup(&chan->notifier); + of_node_put(node); + return ret; +} + +static int tegra_vi_graph_init(struct tegra_vi *vi) +{ + struct tegra_video_device *vid = dev_get_drvdata(vi->client.host); + struct tegra_vi_channel *chan; + struct fwnode_handle *fwnode = dev_fwnode(vi->dev); + int ret; + struct fwnode_handle *remote = NULL; + + /* + * Walk the links to parse the full graph. Each channel will have + * one endpoint of the composite node. Start by parsing the + * composite node and parse the remote entities in turn. + * Each channel will register v4l2 async notifier to make the graph + * independent between the channels so we can the current channel + * in case of something wrong during graph parsing and continue with + * next channels. + */ + list_for_each_entry(chan, &vi->vi_chans, list) { + remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0); + if (!remote) + continue; + + ret = tegra_vi_graph_parse_one(chan, remote); + fwnode_handle_put(remote); + if (ret < 0 || list_empty(&chan->notifier.asd_list)) + continue; + + chan->notifier.ops = &tegra_vi_async_ops; + ret = v4l2_async_notifier_register(&vid->v4l2_dev, + &chan->notifier); + if (ret < 0) { + dev_err(vi->dev, + "failed to register channel %d notifier: %d\n", + chan->portno, ret); + v4l2_async_notifier_cleanup(&chan->notifier); + } + } + + return 0; +} + +static void tegra_vi_graph_cleanup(struct tegra_vi *vi) +{ + struct tegra_vi_channel *chan; + + list_for_each_entry(chan, &vi->vi_chans, list) { + vb2_video_unregister_device(&chan->video); + v4l2_async_notifier_unregister(&chan->notifier); + v4l2_async_notifier_cleanup(&chan->notifier); + } +} + static int tegra_vi_init(struct host1x_client *client) { struct tegra_video_device *vid = dev_get_drvdata(client->host); @@ -922,13 +1484,14 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto free_chans; - } + else + ret = tegra_vi_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate vi channels: %d\n", ret); + goto free_chans; } ret = tegra_vi_channels_init(vi); @@ -937,6 +1500,12 @@ static int tegra_vi_init(struct host1x_client *client) vid->vi = vi; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_graph_init(vi); + if (ret < 0) + goto free_chans; + } + return 0; free_chans: @@ -950,6 +1519,8 @@ static int tegra_vi_init(struct host1x_client *client) static int tegra_vi_exit(struct host1x_client *client) { + struct tegra_vi *vi = host1x_client_to_vi(client); + /* * Do not cleanup the channels here as application might still be * holding video device nodes. Channels cleanup will happen during @@ -957,6 +1528,9 @@ static int tegra_vi_exit(struct host1x_client *client) * device nodes are released. */ + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_vi_graph_cleanup(vi); + return 0; } diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index 6272c9a..7d6b7a6 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,19 @@ struct tegra_vi { }; /** + * struct tegra_vi_graph_entity - Entity in the video graph + * + * @asd: subdev asynchronous registration information + * @entity: media entity from the corresponding V4L2 subdev + * @subdev: V4L2 subdev + */ +struct tegra_vi_graph_entity { + struct v4l2_async_subdev asd; + struct media_entity *entity; + struct v4l2_subdev *subdev; +}; + +/** * struct tegra_vi_channel - Tegra video channel * * @list: list head for this entry @@ -138,10 +152,13 @@ struct tegra_vi { * @done_lock: protects the capture done queue list * * @portno: VI channel port number + * @of_node: device node of VI channel * * @ctrl_handler: V4L2 control handler of this video channel + * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats * @tpg_fmts_bitmap: a bitmap for supported TPG formats * @pg_mode: test pattern generator mode (disabled/direct/patch) + * @notifier: V4L2 asynchronous subdevs notifier */ struct tegra_vi_channel { struct list_head list; @@ -174,10 +191,14 @@ struct tegra_vi_channel { spinlock_t done_lock; unsigned char portno; + struct device_node *of_node; struct v4l2_ctrl_handler ctrl_handler; + DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); enum tegra_vi_pg_mode pg_mode; + + struct v4l2_async_notifier notifier; }; /** @@ -249,7 +270,9 @@ extern const struct tegra_vi_soc tegra210_vi_soc; #endif struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan); +tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); +struct v4l2_subdev * +tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); void tegra_channel_release_buffers(struct tegra_vi_channel *chan, enum vb2_buffer_state state); From patchwork Thu Jul 23 23:51:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65791 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyks2-00AkL4-UF; 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Thu, 23 Jul 2020 23:48:23 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:23 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 11/14] media: tegra-video: Add support for selection ioctl ops Date: Thu, 23 Jul 2020 16:51:09 -0700 Message-ID: <1595548272-9809-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548040; bh=Ox1xqzUlosOFJz7AkHpjytVJAyKTPw61x1/P1FNIrJo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=pw6rfqtK5pEnnLHACqIhUYArv09+zA2lD0RPzm44jbkhijbIcx0+0G2BkdD+/8IEX pL3lYZTC4mZOQiSVHFhGkozzFRlAgBaCNIGPZYgKCYW2kBZ/RP8hxd+oYDUSsvsTlJ kvqQr6ZaJEOJF52TU/qwuR3lV4czL9f+4z9WJseOUSr6brheBwYXXwm/MmtZQvMA/k esD3KoWsM8C1qKLEM7L863VbyOueORjJImNeWL5/58++0JI++VLUX6Rtnf5baA1Y9r 6TG0GEsup6THTN7Oit/jf8g9xxRuYiSkSde2SUTeOBJArfSwNZkctiOlcCqeNLny7N JrYaQQBTqo1bw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds selection v4l2 ioctl operations to allow configuring a selection rectangle in the sensor through the Tegra video device node. Some sensor drivers supporting crop uses try_crop rectangle from v4l2_subdev_pad_config during try format for computing binning. So with selection ops support, this patch also updates try format to use try crop rectangle either from subdev frame size enumeration or from subdev crop boundary. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index f7dbea2..fc43629 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -437,6 +437,13 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + struct v4l2_subdev_frame_size_enum fse = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = V4L2_SEL_TGT_CROP_BOUNDS, + }; int ret; subdev = tegra_channel_get_remote_source_subdev(chan); @@ -462,6 +469,24 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); + + /* + * Attempt to obtain the format size from subdev. + * If not available, try to get crop boundary from subdev. + */ + fse.code = fmtinfo->code; + ret = v4l2_subdev_call(subdev, pad, enum_frame_size, pad_cfg, &fse); + if (ret) { + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (ret) + return -EINVAL; + pad_cfg->try_crop.width = sdsel.r.width; + pad_cfg->try_crop.height = sdsel.r.height; + } else { + pad_cfg->try_crop.width = fse.max_width; + pad_cfg->try_crop.height = fse.max_height; + } + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); if (ret < 0) return ret; @@ -551,6 +576,85 @@ static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) return 0; } +static int tegra_channel_g_selection(struct file *file, void *priv, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + }; + int ret; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, get_selection)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + /* + * Try the get selection operation and fallback to get format if not + * implemented. + */ + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (!ret) + sel->r = sdsel.r; + if (ret != -ENOIOCTLCMD) + return ret; + + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret < 0) + return ret; + + sel->r.left = 0; + sel->r.top = 0; + sel->r.width = fmt.format.width; + sel->r.height = fmt.format.height; + + return 0; +} + +static int tegra_channel_s_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + int ret; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + .flags = sel->flags, + .r = sel->r, + }; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, set_selection)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vb2_is_busy(&chan->queue)) + return -EBUSY; + + ret = v4l2_subdev_call(subdev, pad, set_selection, NULL, &sdsel); + if (!ret) { + sel->r = sdsel.r; + /* + * Subdev active format resolution may have changed during + * set selection operation. So, update channel format to + * the sub-device active format. + */ + return tegra_channel_set_subdev_active_fmt(chan); + } + + return ret; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { @@ -608,6 +712,8 @@ static const struct v4l2_ioctl_ops tegra_channel_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_g_selection = tegra_channel_g_selection, + .vidioc_s_selection = tegra_channel_s_selection, }; /* From patchwork Thu Jul 23 23:51:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65792 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyks7-00AkL4-K1; Thu, 23 Jul 2020 23:43:32 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728455AbgGWXs1 (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:27 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17670 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728194AbgGWXsY (ORCPT ); Thu, 23 Jul 2020 19:48:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:46:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:24 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:24 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:23 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:24 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:23 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 12/14] gpu: host1x: mipi: Keep MIPI clock enabled till calibration is done Date: Thu, 23 Jul 2020 16:51:10 -0700 Message-ID: <1595548272-9809-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595547982; bh=7YV/RNdP1EunzTF6v813MxrmrehBVahzPQ0dOJiVOQI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lPY06tsV1yznzgcV1NJv5wMTVHuEMKfbRCpAOlQspYzyhVryp+DpUGyqYg2py+vjr UqTglK/3ktfcUczi6uZDEcNZi22hvOizSde3PMJXGePW9QMeZYkl1kQfrCoD/s6iqt zP4qpSPKeQajje477NN/a6PF5uuDBcDmHRgZuy555kKq2ziOcMvAu3HEWNN5eZ7LAv l0Eo06HH2GmP5W+rNCEi0FDgR+ZjandOkY0z2x/f/CAavhs+ntejWT9MNn1ltCWjdW 1MnNxsH5zkY1qkg4iL+ro+7CB8Xm3sjdkoTX2+y6pywaXCPLly8cJPQTgm52SIuycJ fj+xUKW4bODxw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no With the split of MIPI calibration into tegra_mipi_calibrate() and tegra_mipi_wait(), MIPI clock is not kept enabled till the calibration is done. So, this patch skips disabling MIPI clock after triggering start of calibration and disables it only after waiting for done status from the calibration logic. This patch renames tegra_mipi_calibrate() as tegra_mipi_start_calibration() and tegra_mipi_wait() as tegra_mipi_finish_calibration() to be inline with their usage. As MIPI clock is left enabled and in case of any failures with CSI input streaming tegra_mipi_finish_calibration() will not get invoked. So added new API tegra_mipi_cancel_calibrate() which disables MIPI clock and consumer drivers can call this in such cases. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/drm/tegra/dsi.c | 4 ++-- drivers/gpu/host1x/mipi.c | 19 ++++++++++--------- include/linux/host1x.h | 5 +++-- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 3820e8d..4d54c13 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -694,11 +694,11 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err = tegra_mipi_calibrate(dsi->mipi); + err = tegra_mipi_start_calibrate(dsi->mipi); if (err < 0) return err; - return tegra_mipi_wait(dsi->mipi); + return tegra_mipi_finish_calibrate(dsi->mipi); } static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e606464..f06c5cd 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -293,17 +293,19 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) } EXPORT_SYMBOL(tegra_mipi_disable); -int tegra_mipi_wait(struct tegra_mipi_device *device) +void tegra_mipi_cancel_calibrate(struct tegra_mipi_device *device) +{ + clk_disable(device->mipi->clk); +} +EXPORT_SYMBOL(tegra_mipi_cancel_calibrate); + +int tegra_mipi_finish_calibrate(struct tegra_mipi_device *device) { struct tegra_mipi *mipi = device->mipi; void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2); u32 value; int err; - err = clk_enable(device->mipi->clk); - if (err < 0) - return err; - mutex_lock(&device->mipi->lock); err = readl_relaxed_poll_timeout(status_reg, value, @@ -315,9 +317,9 @@ int tegra_mipi_wait(struct tegra_mipi_device *device) return err; } -EXPORT_SYMBOL(tegra_mipi_wait); +EXPORT_SYMBOL(tegra_mipi_finish_calibrate); -int tegra_mipi_calibrate(struct tegra_mipi_device *device) +int tegra_mipi_start_calibrate(struct tegra_mipi_device *device) { const struct tegra_mipi_soc *soc = device->mipi->soc; unsigned int i; @@ -382,11 +384,10 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); mutex_unlock(&device->mipi->lock); - clk_disable(device->mipi->clk); return 0; } -EXPORT_SYMBOL(tegra_mipi_calibrate); +EXPORT_SYMBOL(tegra_mipi_start_calibrate); static const struct tegra_mipi_pad tegra114_mipi_pads[] = { { .data = MIPI_CAL_CONFIG_CSIA }, diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 20c885d..0065763 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -333,7 +333,8 @@ struct tegra_mipi_device *tegra_mipi_request(struct device *device, void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); -int tegra_mipi_calibrate(struct tegra_mipi_device *device); -int tegra_mipi_wait(struct tegra_mipi_device *device); +int tegra_mipi_start_calibrate(struct tegra_mipi_device *device); +int tegra_mipi_finish_calibrate(struct tegra_mipi_device *device); +void tegra_mipi_cancel_calibrate(struct tegra_mipi_device *device); #endif From patchwork Thu Jul 23 23:51:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65794 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksL-00AkMB-81; Thu, 23 Jul 2020 23:43:46 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728515AbgGWXst (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:49 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17677 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728436AbgGWXsZ (ORCPT ); Thu, 23 Jul 2020 19:48:25 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:46:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:25 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:25 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:24 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:24 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:24 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 13/14] media: tegra-video: Add CSI MIPI pads calibration Date: Thu, 23 Jul 2020 16:51:11 -0700 Message-ID: <1595548272-9809-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595547982; bh=g/Xy/d2Bic8K6LHFyDmy9eFDrmnaUyUj6fM56xzP/94=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=C8Jwmp2OJKie2fYU50Er2dsmF4o9TScDvaQ1cKwbC1h4SbAey8f23belzzX8KYbkP lwq0k5AFbsY9B0MXzXkvh3tjnbN13CeqBYG82gAsk7HgZc2AZ+7ylAU0MZC3mLMB5V 3WBFwLJ+jNJi3xPpBVH2Y/FBzCgG2IcY7ZmAEqGSOdM5vkOkgYIbNJGh5SykmXjiMU QsMp4IL1amGK63NiXpPtLkcrFmBToEbtA7s1budxxZpoSroAwMCQ1Y6nlNIUi3/FNc jFku+X7AVxPm4FqTA4IwCggwalTaFbUd3yKv+OpzP+qh4kkU4Xwm46yuSMqrRy1z7E aTB85LtY705bw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no CSI MIPI pads need to be enabled and calibrated for capturing from the external sensor or transmitter. MIPI CAL unit calibrates MIPI pads pull-up, pull-down and termination impedances. Calibration is done by co-work of MIPI BIAS pad and MIPI CAL control unit. Triggering calibration start can happen any time after MIPI pads are enabled but calibration results will be latched and applied to MIPI pads by MIPI CAL unit only when the link is in LP11 state and then calibration status register gets updated. This patch enables CSI MIPI pads and calibrates them during streaming. Tegra CSI receiver is able to catch the very first clock transition. So, CSI receiver is always enabled prior to sensor streaming and trigger of calibration start is done during CSI subdev streaming and status of calibration is verified after sensor stream on. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 55 +++++++++++++++++++++++++++++++-- drivers/staging/media/tegra-video/csi.h | 2 ++ drivers/staging/media/tegra-video/vi.c | 25 ++++++++++++++- 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index c21dd09..bdaf4b6 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -252,15 +252,51 @@ static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) return ret; } + if (csi_chan->mipi) { + ret = tegra_mipi_enable(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to enable MIPI pads: %d\n", + ret); + goto rpm_put; + } + + /* + * CSI MIPI pads PULLUP, PULLDN and TERM impedances + * need to be calibrated after power on. + * So, trigger the calibration start here and results + * will be latched and applied to the pads when link is + * in LP11 state during start of sensor streaming. + */ + ret = tegra_mipi_start_calibrate(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to start MIPI calibrate: %d\n", + ret); + goto disable_mipi; + } + } + ret = csi->ops->csi_start_streaming(csi_chan); - if (ret < 0) - goto rpm_put; + if (ret < 0) { + if (csi_chan->mipi) + tegra_mipi_cancel_calibrate(csi_chan->mipi); + goto disable_mipi; + } return 0; } csi->ops->csi_stop_streaming(csi_chan); +disable_mipi: + if (csi_chan->mipi) { + ret = tegra_mipi_disable(csi_chan->mipi); + if (ret < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", ret); + } + rpm_put: pm_runtime_put(csi->dev); return ret; @@ -294,6 +330,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; + int ret = 0; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -312,7 +349,16 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; } - return 0; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + chan->mipi = tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret = PTR_ERR(chan->mipi); + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } + + return ret; } static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) @@ -475,6 +521,9 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) struct tegra_csi_channel *chan, *tmp; list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { + if (chan->mipi) + tegra_mipi_free(chan->mipi); + subdev = &chan->subdev; if (subdev->dev) { if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 78a5110..0d50fc3 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -50,6 +50,7 @@ struct tegra_csi; * @framerate: active framerate for TPG * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format + * @mipi: mipi device for corresponding csi channel pads */ struct tegra_csi_channel { struct list_head list; @@ -65,6 +66,7 @@ struct tegra_csi_channel { unsigned int framerate; unsigned int h_blank; unsigned int v_blank; + struct tegra_mipi_device *mipi; }; /** diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index fc43629..129790c 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -191,10 +191,12 @@ tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan) int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { struct v4l2_subdev *subdev, *csi_subdev, *src_subdev; + struct tegra_csi_channel *csi_chan; int ret; csi_subdev = tegra_channel_get_remote_csi_subdev(chan); src_subdev = tegra_channel_get_remote_source_subdev(chan); + csi_chan = v4l2_get_subdevdata(csi_subdev); /* * Tegra CSI receiver can detect the first LP to HS transition. * So, start the CSI stream-on prior to sensor stream-on and @@ -208,10 +210,31 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) return 0; + /* + * TRM has incorrectly documented to wait for done status from + * calibration logic after CSI interface power on. + * As per the design, calibration results are latched and applied + * to the pads only when the link is in LP11 state which will happen + * during the sensor stream-on. + * CSI subdev stream-on triggers start of MIPI pads calibration. + * Wait for calibration to finish here after sensor subdev stream-on + * and in case of sensor stream-on failure, cancel the calibration. + */ subdev = on ? src_subdev : csi_subdev; ret = v4l2_subdev_call(subdev, video, s_stream, on); - if (ret < 0 && ret != -ENOIOCTLCMD) + if (ret < 0 && ret != -ENOIOCTLCMD) { + if (on && csi_chan->mipi) + tegra_mipi_cancel_calibrate(csi_chan->mipi); return ret; + } + + if (on && csi_chan->mipi) { + ret = tegra_mipi_finish_calibrate(csi_chan->mipi); + if (ret < 0) + dev_err(csi_chan->csi->dev, + "MIPI calibration failed: %d\n", ret); + return ret; + } return 0; } From patchwork Thu Jul 23 23:51:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65793 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jyksJ-00AkMB-1g; Thu, 23 Jul 2020 23:43:43 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728498AbgGWXsm (ORCPT + 1 other); Thu, 23 Jul 2020 19:48:42 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18029 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728443AbgGWXs0 (ORCPT ); Thu, 23 Jul 2020 19:48:26 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 16:47:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 16:48:25 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 16:48:25 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 23:48:25 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 23:48:25 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.236]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 16:48:25 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v4 14/14] media: tegra-video: Compute settle times based on the clock rate Date: Thu, 23 Jul 2020 16:51:12 -0700 Message-ID: <1595548272-9809-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595548042; bh=O7OwfDPtrwAESPcnfY4hKzGwmLiXVBIun9uDnAHRy8A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=pSQ8GFpqxEWtPJ/mDxNYWfdMYH/vSWcyh5Ie07qLwLaZsj5+1puw4d2MV+LrANtsX q8Z9NTMvScBgEWw9BZUzTkSlyKiIEsNJroa6vMwqv7keDF/TbkfeknIqajSRevG8ag e0DbXQfEy9Z/AqyySFpbQ9Um2z6BrCrdaR4G2P9Z8gjD3KcZz0bazpFCOTd2XEHAYz hId73TVKorux1hM2FQk09TeyL4cHT/0+4wcNOGah4/J1I9NBjN9jDbJ1G58z1qBe0p XWCCoWUq7Z7vsMT2iyhmgVruDL1epc8qSC55CL+vu6dnUmqmeBhGjXuGqDmT/66dz0 k7+/ck+XKIRfA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Settle time determines the number of cil clock cyles to wait after LP00 when moving from LP to HS. This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil clock rate and pixel rate from the sensor and programs them during streaming. T-CLK-SETTLE time is the interval during which receiver will ignore any HS transitions on clock lane starting from the beginning of T-CLK-PREPARE. T-HS-SETTLE time is the interval during which recevier will ignore any HS transitions on data lane starting from the beginning of T-HS-PREPARE. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 55 ++++++++++++++++++++++++++++ drivers/staging/media/tegra-video/csi.h | 5 +++ drivers/staging/media/tegra-video/tegra210.c | 17 ++++++++- 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index bdaf4b6..4d38e0e 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -19,6 +19,8 @@ #include "csi.h" #include "video.h" +#define MHZ 1000000 + static inline struct tegra_csi * host1x_client_to_csi(struct host1x_client *client) { @@ -235,6 +237,59 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } +static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) +{ + struct tegra_vi_channel *chan; + struct v4l2_subdev *src_subdev; + struct v4l2_ctrl *ctrl; + + chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); + if (ctrl) + return v4l2_ctrl_g_ctrl_int64(ctrl); + + return 0; +} + +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time) +{ + struct tegra_csi *csi = csi_chan->csi; + unsigned int cil_clk_mhz; + unsigned int pix_clk_mhz; + int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + + cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; + pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; + + /* + * CLK Settle time is the interval during which HS receiver should + * ignore any clock lane HS transitions, starting from the beginning + * of T-CLK-PREPARE. + * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns + * + * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns + * midpoint = 197.5 ns + */ + *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; + + /* + * THS Settle time is the interval during which HS receiver should + * ignore any data lane HS transitions, starting from the beginning + * of THS-PREPARE. + * + * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI + * and 145ns+10UI. + * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI + * midpoint = 115ns + 8UI + */ + if (pix_clk_mhz) + *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz + / (2 * pix_clk_mhz) - 5000) / 1000; +} + static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 0d50fc3..c65ff73 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -51,6 +51,7 @@ struct tegra_csi; * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format * @mipi: mipi device for corresponding csi channel pads + * @pixel_rate: active pixel rate from the sensor on this channel */ struct tegra_csi_channel { struct list_head list; @@ -67,6 +68,7 @@ struct tegra_csi_channel { unsigned int h_blank; unsigned int v_blank; struct tegra_mipi_device *mipi; + unsigned int pixel_rate; }; /** @@ -147,4 +149,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; #endif void tegra_csi_error_recover(struct v4l2_subdev *subdev); +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 253bf33..ac066c0 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -7,6 +7,7 @@ * This source file contains Tegra210 supported video formats, * VI and CSI SoC specific data, operations and registers accessors. */ +#include #include #include #include @@ -98,6 +99,8 @@ #define BRICK_CLOCK_B_4X (0x2 << 16) #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 +#define CLK_SETTLE_MASK GENMASK(13, 8) +#define THS_SETTLE_MASK GENMASK(5, 0) #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c #define TEGRA_CSI_CIL_STATUS 0x010 #define TEGRA_CSI_CILX_STATUS 0x014 @@ -770,8 +773,14 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) { struct tegra_csi *csi = csi_chan->csi; unsigned int portno = csi_chan->csi_port_num; + u8 clk_settle_time = 0; + u8 ths_settle_time = 10; u32 val; + if (!csi_chan->pg_mode) + tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + &ths_settle_time); + csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); /* clean up status */ @@ -782,7 +791,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) /* CIL PHY registers setup */ cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); - cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); /* * The CSI unit provides for connection of up to six cameras in @@ -801,7 +812,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) BRICK_CLOCK_A_4X); cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); - cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); } else {