From patchwork Wed Jul 15 04:20:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65497 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYps-00Fbqb-9T; Wed, 15 Jul 2020 04:16:00 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728082AbgGOETZ (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:25 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4596 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725824AbgGOETX (ORCPT ); Wed, 15 Jul 2020 00:19:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:23 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:23 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:22 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:22 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 01/18] dt-bindings: i2c: tegra: Document Tegra210 VI I2C clocks and power-domains Date: Tue, 14 Jul 2020 21:20:38 -0700 Message-ID: <1594786855-26506-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786750; bh=M4O0xvH9jkOkIfyCWsWjZaEplFLrJZlC+QemXhCNkTI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Q4sNDhf7qMcqUTgPnN0JSwr1ga81wkG28Btq//uewCuxbpPCfCTpeZ0ylf4jHgazr F4uaS1/2O1Sda8TS/+HpVw+SnYsth8tsPUwe+f/bcWJvYnGPHcitFhHCb9ggAuWrDL aUsVbO5kH6zqAO9CS36SLldto9VpyOuGFRFBQiosdunr65Bo1nTllPjpGytFrRmaeX 7lfbmz32Xe5+QYVs2WFAYWNBdHPzm5Pt07aF0LY9Fx+yr8aUUX6LNq9KvGd04/RhJg AUfUKLgBiLFYp93sBRU3nde3fAvNYgwiiobctzmI5rZqwxHJ7ZqYk4jhHWI6txGH/b 4U5b2duBBKfhA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch documents missing clocks and power-domains of Tegra210 VI I2C. Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt index 18c0de3..3f2f990 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt @@ -35,12 +35,12 @@ Required properties: Due to above changes, Tegra114 I2C driver makes incompatible with previous hardware driver. Hence, tegra114 I2C controller is compatible with "nvidia,tegra114-i2c". - nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the - host1x domain and typically used for camera use-cases. This VI I2C - controller is mostly compatible with the programming model of the - regular I2C controllers with a few exceptions. The I2C registers start - at an offset of 0xc00 (instead of 0), registers are 16 bytes apart - (rather than 4) and the controller does not support slave mode. + nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus + and is part of VE power domain and typically used for camera use-cases. + This VI I2C controller is mostly compatible with the programming model + of the regular I2C controllers with a few exceptions. The I2C registers + start at an offset of 0xc00 (instead of 0), registers are 16 bytes + apart (rather than 4) and the controller does not support slave mode. - reg: Should contain I2C controller registers physical address and length. - interrupts: Should contain I2C controller interrupts. - address-cells: Address cells for I2C device address. @@ -53,10 +53,17 @@ Required properties: - fast-clk Tegra114: - div-clk + Tegra210: + - div-clk + - slow (only for nvidia,tegra210-i2c-vi compatible node) - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - i2c +- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must + include venc powergate node as vi i2c is part of VE power domain. + tegra210-i2c-vi: + - pd_venc - dmas: Must contain an entry for each entry in clock-names. See ../dma/dma.txt for details. - dma-names: Must include the following entries: From patchwork Wed Jul 15 04:20:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65480 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYoT-00FbmP-6F; Wed, 15 Jul 2020 04:14:33 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728115AbgGOET0 (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:26 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11959 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728083AbgGOETZ (ORCPT ); Wed, 15 Jul 2020 00:19:25 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:18:27 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:25 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:25 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:24 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:23 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:23 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 02/18] arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C Date: Tue, 14 Jul 2020 21:20:39 -0700 Message-ID: <1594786855-26506-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786707; bh=v4jvA2ws+jGeq8HdlC90J3dYqc1EOn/BsdDD724mHAI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ps9SuL2oJb6j75CIHNyrdHhd8UbkFrZxe1WCcnOux6mjctjrGze2iciHUErXkDdqB CIj1unXhv4hoWgrj2gNEQmqNym3te8EAgNc1asHC3vkbrk0g9u/XIncj2LMv9avzMa WOM8vrkTAtimHYPNevpW6qC8nwAtQpYgMo9uDcZH9zjOxIGk01laX7cPjGek+GTLQi 2hu7Jm1tRwG6Z1ppc69lKOrRvNTT0VJdCzCkIh2t1TaIBYdbOLl0nZV49BxpDDROFq v34Z86aRTBjucbb/52qeeIX/S7+zcPHJc+qP1vwVQqbkhXwyRurq7Hlrwp3utxOoGw wmQ0jAxNnxo7Q== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra210 VI I2C is in VE power domain and i2c-vi node should have power-domains property. Current Tegra210 i2c-vi device node is missing both VI I2C clocks and power-domains property. This patch adds them. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f4e0cc2..3827e43 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -375,6 +375,12 @@ compatible = "nvidia,tegra210-i2c-vi"; reg = <0x0 0x546c0000 0x0 0x00040000>; interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, + <&tegra_car TEGRA210_CLK_I2CSLOW>; + clock-names = "div-clk", "slow"; + resets = <&tegra_car TEGRA210_CLK_VI_I2C>; + reset-names = "i2c"; + power-domains = <&pd_venc>; status = "disabled"; }; }; From patchwork Wed Jul 15 04:20:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65495 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpn-00FbqA-Bg; Wed, 15 Jul 2020 04:15:55 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728874AbgGOEUq (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:46 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9559 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728103AbgGOET0 (ORCPT ); Wed, 15 Jul 2020 00:19:26 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:25 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:25 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:25 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:24 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:24 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 03/18] i2c: tegra: Don't mark VI I2C as IRQ safe runtime PM Date: Tue, 14 Jul 2020 21:20:40 -0700 Message-ID: <1594786855-26506-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786652; bh=zxB65TqmmcKmPfWkLJU50AtZToCBrCGEYlb/JsyjY+U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Xka7PEDQWikb4oQIXRaCkY2gULdhMDJ1lasgdot1PE7Qf8Z/hdMS8RhHveHp+qBk+ P7VgFglkANZ11RbdOM7SOFc/cLmigsqV9PcSWWJVYFBnIPYPeLfDz9pX9xSI3K1MDi QOeJzMMya50BETGQiaSeB2mhYEW/QqRUFqK5F7OCpeM+SG+yfLlCVzLWUN47dMsJN5 4tGMIVKVP/LW642IIzNsh5ze1UW2iMBZKLmdO9mwC03T6WBX3O4FDnA0MgQw0sKr29 eLagY03vZ1rKnriR7npLuBZ5bKSQfO8Kgisz1Yg0mTYzoCCEERwMpbqm+eW6BKOmNO 6Iwvh4+fpTNUA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra VI I2C is part of VE power domain and typically used for camera usecases. VE power domain is not always on and is non-IRQ safe. So, IRQ safe device cannot be attached to a non-IRQ safe domain as it prevents powering off the PM domain and generic power domain driver will warn. Current driver marks all I2C devices as IRQ safe and VI I2C device does not require IRQ safe as it will not be used for atomic transfers. This patch has fix to make VI I2C as non-IRQ safe. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1577296..3be1018 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1750,7 +1750,15 @@ static int tegra_i2c_probe(struct platform_device *pdev) goto unprepare_slow_clk; } - pm_runtime_irq_safe(&pdev->dev); + /* + * VI I2C is in VE power domain which is not always on and not + * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ + * safe domain as it prevents powering off the PM domain. + * Also, VI I2C device don't need to use runtime IRQ safe as it will + * not be used for atomic transfers. + */ + if (!i2c_dev->is_vi) + pm_runtime_irq_safe(&pdev->dev); pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { ret = tegra_i2c_runtime_resume(&pdev->dev); From patchwork Wed Jul 15 04:20:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65496 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpo-00FbqA-EO; Wed, 15 Jul 2020 04:15:57 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728867AbgGOEUq (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:46 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4601 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728112AbgGOET1 (ORCPT ); Wed, 15 Jul 2020 00:19:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:26 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:26 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:26 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:25 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 04/18] i2c: tegra: Remove NULL pointer check before clk_enable/disable/prepare/unprepare Date: Tue, 14 Jul 2020 21:20:41 -0700 Message-ID: <1594786855-26506-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786754; bh=K1cqc1lt5rx1omIWXrbpyHIFcL/GVkgfSPNdjEnFEXk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rvBoNDycTrsqvlmI/4/NtlrV6CRGHe3zSxK+cM1+PvlVP34uyEOpP+8MYz7JSIA0I IJW4koQ9SUnnDcT2nsT2COn1HOTuVWovEaYFU/8clgodg/FUK/joYjpVVfnje3+jGk TVxJNuPGP0nVjuX8qlM66BCASFNfEyb1CsTw01yhrkdv5EZ23iLBhcPukapummePGE N58btaAvWPpICqtJRm+WtBSQxZbQCNT8mwyT8lNPBKZysA/1E0MuH5boi/Nc58KdNC I+bAIUx2gdJZYtJSsyaEf3BJmYwDR2g5fznJFc6Bf0x+jpgtlSheUnfyP3Hnpct0PU Hzs/zrEjlnIpA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no clk_enable, clk_disable, clk_prepare, and clk_unprepare APIs have implementation for checking clk pointer not NULL and clock consumers can safely call these APIs without NULL pointer check. So, this patch cleans up Tegra i2c driver to remove explicit checks before these APIs. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 64 +++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3be1018..c91307b9 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -655,21 +655,17 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) if (ret) return ret; - if (!i2c_dev->hw->has_single_clk_source) { - ret = clk_enable(i2c_dev->fast_clk); - if (ret < 0) { - dev_err(i2c_dev->dev, - "Enabling fast clk failed, err %d\n", ret); - return ret; - } + ret = clk_enable(i2c_dev->fast_clk); + if (ret < 0) { + dev_err(i2c_dev->dev, + "Enabling fast clk failed, err %d\n", ret); + return ret; } - if (i2c_dev->slow_clk) { - ret = clk_enable(i2c_dev->slow_clk); - if (ret < 0) { - dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; - } + ret = clk_enable(i2c_dev->slow_clk); + if (ret < 0) { + dev_err(dev, "failed to enable slow clock: %d\n", ret); + return ret; } ret = clk_enable(i2c_dev->div_clk); @@ -688,12 +684,8 @@ static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); clk_disable(i2c_dev->div_clk); - - if (i2c_dev->slow_clk) - clk_disable(i2c_dev->slow_clk); - - if (!i2c_dev->hw->has_single_clk_source) - clk_disable(i2c_dev->fast_clk); + clk_disable(i2c_dev->slow_clk); + clk_disable(i2c_dev->fast_clk); return pinctrl_pm_select_idle_state(i2c_dev->dev); } @@ -1716,20 +1708,16 @@ static int tegra_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, i2c_dev); - if (!i2c_dev->hw->has_single_clk_source) { - ret = clk_prepare(i2c_dev->fast_clk); - if (ret < 0) { - dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); - return ret; - } + ret = clk_prepare(i2c_dev->fast_clk); + if (ret < 0) { + dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); + return ret; } - if (i2c_dev->slow_clk) { - ret = clk_prepare(i2c_dev->slow_clk); - if (ret < 0) { - dev_err(dev, "failed to prepare slow clock: %d\n", ret); - goto unprepare_fast_clk; - } + ret = clk_prepare(i2c_dev->slow_clk); + if (ret < 0) { + dev_err(dev, "failed to prepare slow clock: %d\n", ret); + goto unprepare_fast_clk; } if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ && @@ -1843,12 +1831,10 @@ static int tegra_i2c_probe(struct platform_device *pdev) clk_unprepare(i2c_dev->div_clk); unprepare_slow_clk: - if (i2c_dev->is_vi) - clk_unprepare(i2c_dev->slow_clk); + clk_unprepare(i2c_dev->slow_clk); unprepare_fast_clk: - if (!i2c_dev->hw->has_single_clk_source) - clk_unprepare(i2c_dev->fast_clk); + clk_unprepare(i2c_dev->fast_clk); return ret; } @@ -1867,12 +1853,8 @@ static int tegra_i2c_remove(struct platform_device *pdev) tegra_i2c_runtime_suspend(&pdev->dev); clk_unprepare(i2c_dev->div_clk); - - if (i2c_dev->slow_clk) - clk_unprepare(i2c_dev->slow_clk); - - if (!i2c_dev->hw->has_single_clk_source) - clk_unprepare(i2c_dev->fast_clk); + clk_unprepare(i2c_dev->slow_clk); + clk_unprepare(i2c_dev->fast_clk); tegra_i2c_release_dma(i2c_dev); return 0; From patchwork Wed Jul 15 04:20:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65493 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpX-00Fbok-Ju; Wed, 15 Jul 2020 04:15:40 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728218AbgGOET3 (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:29 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11970 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728163AbgGOET2 (ORCPT ); Wed, 15 Jul 2020 00:19:28 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:18:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:27 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:27 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:27 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:27 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:26 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 05/18] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume Date: Tue, 14 Jul 2020 21:20:42 -0700 Message-ID: <1594786855-26506-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786709; bh=eufXsoZ14WkRUf36lqjK6lfwNSwXZDr32mhUx6fHlSE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=O8tYkUqrbIYTKjoF52jmmh2bSQejoxqlnbuovv0mgrgzo6II8YlzvPYBAd0qpzXYx 4Mr2rH0cYU1CUEdI8Mw1loF0qCOKI9IWt3BBBfH9UsyWUTbXP2jZ93HxjLYKBYTQGp 1dt48ep7L7N3fUlZBxlrbNaPSQ+IMC7aLlVtDLsbpaWh8K7hzTJD46eVpLiNuKvqt5 4HOLZujS5elgYo/gRqoTSfHnz49xnCiWHsszGroWL58455IvYUe2TzUlXYafSgEYmD Zn6VVASBbNixVKNCdWXlcfOYzne+uo02TVeL/Q46nSJeS/Ksqpqm+si36vMyQXnecE Phybz8I+sRNyA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no tegra_i2c_runtime_resume does not disable prior enabled clocks properly. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c91307b9..7b93c45 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -665,18 +665,23 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) ret = clk_enable(i2c_dev->slow_clk); if (ret < 0) { dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; + goto disable_fast_clk; } ret = clk_enable(i2c_dev->div_clk); if (ret < 0) { dev_err(i2c_dev->dev, "Enabling div clk failed, err %d\n", ret); - clk_disable(i2c_dev->fast_clk); - return ret; + goto disable_slow_clk; } return 0; + +disable_slow_clk: + clk_disable(i2c_dev->slow_clk); +disable_fast_clk: + clk_disable(i2c_dev->fast_clk); + return ret; } static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) From patchwork Wed Jul 15 04:20:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65494 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpd-00Fbpf-1n; Wed, 15 Jul 2020 04:15:45 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728634AbgGOEUi (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:38 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9565 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728083AbgGOET3 (ORCPT ); Wed, 15 Jul 2020 00:19:29 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:29 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:29 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:28 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:28 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:28 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 06/18] i2c: tegra: Fix runtime resume to re-init VI I2C Date: Tue, 14 Jul 2020 21:20:43 -0700 Message-ID: <1594786855-26506-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786655; bh=rVT7elWIzK6dQfAm9YaBBuoEEleair7GkfBCOrcVb5U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZVsOspQXOQhKMXofQtLcCis5jFnvhNKlwIeOFcdXIxp7MIDcMAY4ro7qygeTxmC4J 6pSo0qCZ29/9V9vh0ZHep15nKCkSRd1OGcBed1u/vUmiVMY0MQsCpYUzjKluVkmkyd rz+Gr/fEJir1zYqLqeLd663lZW057MZVwapgE1Hg7laKvGddSbOJtoMikagAC58xFr 3rC1Ukavenfp8Q+OVxwXC0ae9HnpWcPI8LsTakw94NB6/+nCefVexuVmFZtalrWExe eae7bsKnX6r+4AFGyr4XLZ0BGLVBoYRQicyJ58lG2AG84nt4ZBXLFf22yLBfbfIA35 +X5DZPAwGdmug== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus and is part of VE power domain. During suspend/resume VE power domain goes through power off/on. So, controller reset followed by i2c re-initialization is required after the domain power up. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 7b93c45..1bf3666 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -293,6 +293,8 @@ struct tegra_i2c_dev { bool is_curr_atomic_xfer; }; +static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit); + static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) { @@ -675,8 +677,22 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) goto disable_slow_clk; } + /* + * VI I2C device is attached to VE power domain which goes through + * power ON/OFF during PM runtime resume/suspend. So, controller + * should go through reset and need to re-initialize after power + * domain ON. + */ + if (i2c_dev->is_vi) { + ret = tegra_i2c_init(i2c_dev, true); + if (ret) + goto disable_div_clk; + } + return 0; +disable_div_clk: + clk_disable(i2c_dev->div_clk); disable_slow_clk: clk_disable(i2c_dev->slow_clk); disable_fast_clk: From patchwork Wed Jul 15 04:20:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65492 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpW-00Fbok-Ip; Wed, 15 Jul 2020 04:15:39 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728265AbgGOETd (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:33 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11978 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728232AbgGOETb (ORCPT ); Wed, 15 Jul 2020 00:19:31 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:18:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:30 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:30 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:30 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:29 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:29 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 07/18] i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c Date: Tue, 14 Jul 2020 21:20:44 -0700 Message-ID: <1594786855-26506-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786712; bh=bx39F/3n9Q/pzD3y/Hu3Hjt/owO0zkylWWejNtiAobk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Hc4EcN1U4PoSZ7CTF+0Ivlw7U3QxXpFbGOlGEUEJOZT+WzWzFTVXX/GI7IAoWYwdD iSIeSpVlVntd7fqqw0SaHkLbZCmPEgSP1PQCYpdXlWn9ULWtuULoPkjQe/lY42wLD2 eTniooK6SuhGwED2DlZg+FBH1Jm0la53jmkgSEv1V1RR5JUWcdfSxnPEgFgsx+dmU0 5TFLwrY8xWKy+E0Cyw1aw5+i6xxs64MvX43NAg2SYhUKZdHZNLB5Wi3ExovvdNNhI2 PZljrrUfdkCIO1tPqX0l49TdQ8a4NVQYlhT75DCTtePbqEoBtAekCseyUR5HH75rYV Go1u8whx/1SBA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus so APB DMA can't be used for Tegra210 VI I2C and there are no tx and rx dma channels for VI I2C. So, avoid attempt of requesting DMA channels. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1bf3666..00d3e4d 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -421,7 +421,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) dma_addr_t dma_phys; int err; - if (!i2c_dev->hw->has_apb_dma) + if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) return 0; if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { From patchwork Wed Jul 15 04:20:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65491 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpV-00Fbok-Dq; Wed, 15 Jul 2020 04:15:37 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728288AbgGOETd (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:33 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4615 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728250AbgGOETb (ORCPT ); Wed, 15 Jul 2020 00:19:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:31 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:31 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:30 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 08/18] media: tegra-video: Fix channel format alignment Date: Tue, 14 Jul 2020 21:20:45 -0700 Message-ID: <1594786855-26506-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786759; bh=RezmIyFFbXHYoC7uY1I5ZqbxI3VHo5hil8M0f4GeUvI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=H2PeL/HYEyfKxkIYmT2Z+7rAiSeiBrNlkL8X7wqliMj8OEEz6Em7jYMDJ0MeUvSVk kuWN6ZpkKVLu5gG1aTfABMmio53yhtPx2cvxCGGTNuf/OU7mkkjX9J6gd1Xk+LzSii SC+sIsf7NAn0WmJRLH9J24YABvYGdv3SFxRQYFYeU7qyVYGmwE9TkZVDK1q40E7StD pV/JTfqqOOVCgmCOkydLr66eNDPqmKl3DmNyaeG69gzaMvD7g2/s7piQJsXGHYlkYc oJyhwmLRMOBf0+bsWgNcAVzrAh0maS2xHp/TWUSerzsu+KO6HMNxv1FgHC0iccO3ZN wLYedOEbkAlPw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index a3b9b21..0ae1771 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per From patchwork Wed Jul 15 04:20:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65488 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpK-00FboL-LM; Wed, 15 Jul 2020 04:15:27 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728356AbgGOETg (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:36 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9578 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728262AbgGOETe (ORCPT ); Wed, 15 Jul 2020 00:19:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:39 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:32 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:32 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:32 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:31 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 09/18] media: tegra-video: Enable TPG based on kernel config Date: Tue, 14 Jul 2020 21:20:46 -0700 Message-ID: <1594786855-26506-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786659; bh=IC9MoHLUMSIypQQ5ohPmHwNlDywer31FdsRR/rEIMhM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=NLkwsQRsWKnE9aluw6SrBsgwwl51F6kuyyGoaYWyAOF9Ewayhu35xvbPhCI3/Uu7K 73s6JCpSUOmbNKu6kiWshSVSBiv9RwXnoFNUnKeomQg19BmtF3/NVt5blU65wSC25e haYfmavYMPuP8IEF4kC3BL1u833fNB/PCcg7AKgepo+lzDA+RJKWPFRprIy5RkEqiN 2Shzjo/TT21XN42Z9qskLDBc0LEEHjHJs9qM5XJIAvgIBIac1Hj3AhZot8bcGqGik9 UrZOyMnDyPOySMA01vp9jTwG+Ou3Pk/koqfxfsQ84IeYkRZStqTE62yVr1YVhQViRc eih4GTKf9LSHQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra internal TPG mode is only for Tegra vi and csi testing without a real sensor and driver should default support real sensor. So, This patch adds CONFIG_VIDEO_TEGRA_TPG and enables Tegra internal TPG mode only when this config is selected. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 6 +++++ drivers/staging/media/tegra-video/csi.c | 38 +++++++++++++++++++++++----- drivers/staging/media/tegra-video/tegra210.c | 6 +++++ drivers/staging/media/tegra-video/vi.c | 13 +++++++--- drivers/staging/media/tegra-video/video.c | 23 +++++++++-------- 5 files changed, 65 insertions(+), 21 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index f6c61ec..566da62 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -10,3 +10,9 @@ config VIDEO_TEGRA To compile this driver as a module, choose M here: the module will be called tegra-video. + +config VIDEO_TEGRA_TPG + bool "NVIDIA Tegra VI driver TPG mode" + depends on VIDEO_TEGRA + help + Say yes here to enable Tegra internal TPG mode diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 40ea195..fb667df 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -62,6 +62,9 @@ static int csi_enum_bus_code(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_mbus_code_enum *code) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) return -EINVAL; @@ -76,6 +79,9 @@ static int csi_get_format(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + fmt->format = csi_chan->format; return 0; @@ -121,6 +127,9 @@ static int csi_enum_framesizes(struct v4l2_subdev *subdev, { unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) return -EINVAL; @@ -148,6 +157,9 @@ static int csi_enum_frameintervals(struct v4l2_subdev *subdev, const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; int index; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + /* one framerate per format and resolution */ if (fie->index > 0) return -EINVAL; @@ -172,6 +184,9 @@ static int csi_set_format(struct v4l2_subdev *subdev, const struct v4l2_frmsize_discrete *sizes; unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, ARRAY_SIZE(tegra_csi_tpg_sizes), width, height, @@ -208,6 +223,9 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + vfi->interval.numerator = 1; vfi->interval.denominator = csi_chan->framerate; @@ -311,8 +329,12 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) subdev = &chan->subdev; v4l2_subdev_init(subdev, &tegra_csi_ops); subdev->dev = csi->dev; - snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", - chan->csi_port_num); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", + chan->csi_port_num); + else + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", + kbasename(chan->of_node->full_name)); v4l2_set_subdevdata(subdev, chan); subdev->fwnode = of_fwnode_handle(chan->of_node); @@ -405,11 +427,13 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_csi_tpg_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto cleanup; + } } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3baa4e3..3492a8a 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -631,7 +631,11 @@ const struct tegra_vi_soc tegra210_vi_soc = { .ops = &tegra210_vi_ops, .hw_revision = 3, .vi_max_channels = 6, +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) .vi_max_clk_hz = 499200000, +#else + .vi_max_clk_hz = 998400000, +#endif }; /* Tegra210 CSI PHY registers accessors */ @@ -957,7 +961,9 @@ static const char * const tegra210_csi_cil_clks[] = { "cilab", "cilcd", "cile", +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) "csi_tpg", +#endif }; /* Tegra210 CSI operations */ diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 0ae1771..4ad3da5 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -565,6 +565,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) { int ret; +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) /* add test pattern control handler to v4l2 device */ v4l2_ctrl_new_std_menu_items(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_TEST_PATTERN, @@ -576,6 +577,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#endif /* setup the controls */ ret = v4l2_ctrl_handler_setup(&chan->ctrl_handler); @@ -914,10 +916,13 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, "failed to allocate tpg channels: %d\n", ret); - goto free_chans; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_tpg_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto free_chans; + } } ret = tegra_vi_channels_init(vi); diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/media/tegra-video/video.c index 30816aa..e50bd70 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -60,15 +60,17 @@ static int host1x_video_probe(struct host1x_device *dev) if (ret < 0) goto unregister_v4l2; - /* - * Both vi and csi channels are available now. - * Register v4l2 nodes and create media links for TPG. - */ - ret = tegra_v4l2_nodes_setup_tpg(vid); - if (ret < 0) { - dev_err(&dev->dev, - "failed to setup tpg graph: %d\n", ret); - goto device_exit; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + /* + * Both vi and csi channels are available now. + * Register v4l2 nodes and create media links for TPG. + */ + ret = tegra_v4l2_nodes_setup_tpg(vid); + if (ret < 0) { + dev_err(&dev->dev, + "failed to setup tpg graph: %d\n", ret); + goto device_exit; + } } return 0; @@ -91,7 +93,8 @@ static int host1x_video_remove(struct host1x_device *dev) { struct tegra_video_device *vid = dev_get_drvdata(&dev->dev); - tegra_v4l2_nodes_cleanup_tpg(vid); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_v4l2_nodes_cleanup_tpg(vid); host1x_device_exit(dev); From patchwork Wed Jul 15 04:20:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65489 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpN-00FboX-4Y; Wed, 15 Jul 2020 04:15:29 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728336AbgGOETf (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:35 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9588 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728300AbgGOETe (ORCPT ); Wed, 15 Jul 2020 00:19:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:33 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:33 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:32 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 10/18] media: tegra-video: Update format lookup to offset based Date: Tue, 14 Jul 2020 21:20:47 -0700 Message-ID: <1594786855-26506-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786660; bh=QUTBJM/do+styBTvglomQ9FFF52c6OXaDHHcUb70me0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jco9eVUxuzlotdb29bM+ynD7qYCbFMF/Sedmk1taccVKAClYMiyWtbLKpxqebtRp8 XOLBgbGpCK3Q7kdxD/GTSQa9GrtzmHcEsdfCsxm9LCV5d3CrSqo87Pzo+5Z2EFevL2 XfDBCpQtWLXSR1HT773DlmN+8XMrw88zg7CWl3UTFRlvNAvOD2Ti1Vpm27wjrC120d JEekli3WdFVdWRdtySCLphN0/IbuYVY+PPEHv+Up5TVL4SM908+tBEU2sUmCsQO/4O o1mjO2qTYpjqprgPdqx9hKKXD2WL+Vbr6tWbknCE9jd1tpdTfgBBlhgKyiJ6/We+y9 h+v0m/CBt71Tg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra VI supported video formats are more for non TPG and there can be multiple pixel formats for the same media bus format. This patch updates the helper function for format lookup based on mbus code from pre-defined Tegra supported format list to look from the specified list index offset. Offset based look up is used with sensor device graph (non TPG) where format enumeration can list all supported formats for the specific sensor mbus codes. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 4ad3da5..93edade 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -53,11 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) } static int tegra_get_format_idx_by_code(struct tegra_vi *vi, - unsigned int code) + unsigned int code, + unsigned int offset) { unsigned int i; - for (i = 0; i < vi->soc->nformats; ++i) { + for (i = offset; i < vi->soc->nformats; ++i) { if (vi->soc->video_formats[i].code == code) return i; } @@ -598,11 +599,12 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_zero(chan->tpg_fmts_bitmap, MAX_FORMAT_NUM); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_SRGGB10_1X10); + MEDIA_BUS_FMT_SRGGB10_1X10, 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_RGB888_1X32_PADHI); + MEDIA_BUS_FMT_RGB888_1X32_PADHI, + 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); } From patchwork Wed Jul 15 04:20:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65490 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpU-00Fbok-3X; Wed, 15 Jul 2020 04:15:36 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728841AbgGOEU1 (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:27 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4625 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728332AbgGOETf (ORCPT ); Wed, 15 Jul 2020 00:19:35 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:35 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:35 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:34 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 11/18] dt-bindings: tegra: Update VI and CSI bindings with port info Date: Tue, 14 Jul 2020 21:20:48 -0700 Message-ID: <1594786855-26506-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786762; bh=yGbs5SDi4Dd0+0xT6nDOtBMbjmUT+S0MvKYM2ZVqVhs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ngli1ZjCHCV+7PgXkYKLSX/PDJj9cGBR1ZEY0d6BHlUF0EtD2VR80+MMQY3FFxISt ZRs+Kd2pQpMOi8TufGYjOJyDFAxTt7JKPYdPk6m5H8K7BQBDmOetfFuoJOoBTrWRqU CeayL3MAMII73akRTBVHL4OO1xi0ZS4VBR2PZrQJS3rVcXfjyfoY6KztT486rVaVBq TSPtwvbndRdFRjyLacLon0VqryYYniggIaBONprbvHpUUc4sKehBFSdvhdNroAgJnJ urIXUVBaGeT9EIbxLLQ9L0ifqv9a5Tpr5ImQS3yvpor/SUKgQfs1iShp0BC5FChh+g /2HjJsBTeCUMA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Update VI and CSI bindings to add port and endpoint nodes as per media video-interfaces DT binding document. Signed-off-by: Sowjanya Komatineni Acked-by: Rob Herring --- .../display/tegra/nvidia,tegra20-host1x.txt | 92 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 4731921..ac63ae4a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -51,8 +51,16 @@ of the following host1x client modules: - vi - Tegra210: - power-domains: Must include venc powergate node as vi is in VE partition. - - Tegra210 has CSI part of VI sharing same host interface and register space. - So, VI device node should have CSI child node. + + ports (optional node) + vi can have optional ports node and max 6 ports are supported. Each port + should have single 'endpoint' child node. All port nodes are grouped under + ports node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + csi (required node) + Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. - csi: mipi csi interface to vi @@ -65,6 +73,46 @@ of the following host1x client modules: - power-domains: Must include sor powergate node as csicil is in SOR partition. + channel (optional nodes) + Maximum 6 channels are supported with each csi brick as either x4 or x2 + based on hw connectivity to sensor. + + Required properties: + - reg: csi port number. Valid port numbers are 0 through 5. + - nvidia,mipi-calibrate: Should contain a phandle and a specifier + specifying which pads are used by this CSI port and need to be + calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. + + Each channel node must contain 2 port nodes which can be grouped + under 'ports' node and each port should have a single child 'endpoint' + node. + + ports node + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + ports node must contain below 2 port nodes. + port@0 with single child 'endpoint' node always a sink. + port@1 with single child 'endpoint' node always a source. + + port@0 (required node) + Required properties: + - reg: 0 + + endpoint (required node) + Required properties: + - data-lanes: an array of data lane from 1 to 4. Valid array + lengths are 1/2/4. + - remote-endpoint: phandle to sensor 'endpoint' node. + + port@1 (required node) + Required properties: + - reg: 1 + + endpoint (required node) + Required properties: + - remote-endpoint: phandle to vi port 'endpoint' node. + - epp: encoder pre-processor Required properties: @@ -340,6 +388,18 @@ Example: ranges = <0x0 0x0 0x54080000 0x2000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_vi_in0: endpoint { + remote-endpoint = <&imx219_csi_out0>; + }; + }; + }; + csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; @@ -362,6 +422,34 @@ Example: <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + nvidia,mipi-calibrate = <&mipi 0x001>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_csi_in0: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&imx219_out0>; + }; + }; + + port@1 { + reg = <1>; + imx219_csi_out0: endpoint { + remote-endpoint = <&imx219_vi_in0>; + }; + }; + }; + }; }; }; From patchwork Wed Jul 15 04:20:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65487 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYpG-00Fbo8-L2; Wed, 15 Jul 2020 04:15:24 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728534AbgGOEUP (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:15 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9593 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728376AbgGOETi (ORCPT ); Wed, 15 Jul 2020 00:19:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:36 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:35 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 12/18] media: tegra-video: Add support for external sensor capture Date: Tue, 14 Jul 2020 21:20:49 -0700 Message-ID: <1594786855-26506-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786662; bh=XLiaYWrpb2KeNEx61Nvk8gvKtagtk8IHj0Myq6ApUb8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IjKk6aVNNnY3JCo6kE72q7g5CeTnIazyIindNIbYyUjhGHkrKp+V/hF/X4tggC2f2 7AdWw92YNE+GCxUECl9g8UcYD9okKeviaMVxZkhFCAR0jQWzeK6hhQX6fLkuGAUQz/ MsXjIE9ng38xg9+Ph2/EwIL3WTbX+9o8Nxhj1N0Y3GQk9KKx1DVZ4WzYggwR1o3jBA 4evq75TyLGKyy2dxCq1aw2dzNsIz9o84BHpoNPh6Z0Z2YsjXXeCM5YraiDZecYPaHC ZQfe431G3q8IT2nr4Zc+l5B2HfcH7po3/+UbHiGgsSV0SbHxCLsc2Cr1h1LPiaHl+h HXn9IQ1IkVL7w== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds support to capture from the external sensor based on device graph in the device tree. Driver walks through the device graph to create media links between the entities and registers and unregisters video devices when the corresponding sub-devices are bound and unbound. Channel formats are enumerated based on available formats from the sensor and the corresponding matched formats from the Tegra supported video formats list. Each Tegra CSI instance can be configured as 4-lane or 2-lane based on supported lane configuration from the sensor through the device tree. Currently this driver supports V4L2 video node centric only. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 1 + drivers/staging/media/tegra-video/csi.c | 130 +++++- drivers/staging/media/tegra-video/csi.h | 1 + drivers/staging/media/tegra-video/tegra210.c | 2 +- drivers/staging/media/tegra-video/vi.c | 648 +++++++++++++++++++++++++-- drivers/staging/media/tegra-video/vi.h | 25 +- 6 files changed, 749 insertions(+), 58 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index 566da62..1f35da4 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -5,6 +5,7 @@ config VIDEO_TEGRA depends on VIDEO_V4L2 select MEDIA_CONTROLLER select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE help Choose this option if you have an NVIDIA Tegra SoC. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index fb667df..c21dd09 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -9,10 +9,13 @@ #include #include #include +#include #include #include #include +#include + #include "csi.h" #include "video.h" @@ -285,26 +288,101 @@ static const struct v4l2_subdev_ops tegra_csi_ops = { .pad = &tegra_csi_pad_ops, }; +static int tegra_csi_channel_alloc(struct tegra_csi *csi, + struct device_node *node, + unsigned int port_num, unsigned int lanes, + unsigned int num_pads) +{ + struct tegra_csi_channel *chan; + + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + list_add_tail(&chan->list, &csi->csi_chans); + chan->csi = csi; + chan->csi_port_num = port_num; + chan->numlanes = lanes; + chan->of_node = node; + chan->numpads = num_pads; + if (num_pads & 0x2) { + chan->pads[0].flags = MEDIA_PAD_FL_SINK; + chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; + } else { + chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + } + + return 0; +} + static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) { struct device_node *node = csi->dev->of_node; unsigned int port_num; - struct tegra_csi_channel *chan; unsigned int tpg_channels = csi->soc->csi_max_channels; + int ret; /* allocate CSI channel for each CSI x2 ports */ for (port_num = 0; port_num < tpg_channels; port_num++) { - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; - - list_add_tail(&chan->list, &csi->csi_chans); - chan->csi = csi; - chan->csi_port_num = port_num; - chan->numlanes = 2; - chan->of_node = node; - chan->numpads = 1; - chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_csi_channels_alloc(struct tegra_csi *csi) +{ + struct device_node *node = csi->dev->of_node; + struct v4l2_fwnode_endpoint v4l2_ep = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + struct fwnode_handle *fwh; + struct device_node *channel; + struct device_node *ep; + unsigned int lanes, portno, num_pads; + int ret; + + for_each_child_of_node(node, channel) { + if (!of_node_name_eq(channel, "channel")) + continue; + + ret = of_property_read_u32(channel, "reg", &portno); + if (ret < 0) + continue; + + if (portno >= csi->soc->csi_max_channels) { + dev_err(csi->dev, "invalid port num %d\n", portno); + return -EINVAL; + } + + ep = of_graph_get_endpoint_by_regs(channel, 0, 0); + if (!ep) + continue; + + fwh = of_fwnode_handle(ep); + ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); + of_node_put(ep); + if (ret) { + dev_err(csi->dev, + "failed to parse v4l2 endpoint: %d\n", ret); + return ret; + } + + lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; + if (!lanes || ((lanes & (lanes - 1)) != 0)) { + dev_err(csi->dev, "invalid data-lanes %d\n", lanes); + return -EINVAL; + } + + num_pads = of_graph_get_endpoint_count(channel); + if (num_pads == TEGRA_CSI_PADS_NUM) { + ret = tegra_csi_channel_alloc(csi, channel, portno, + lanes, num_pads); + if (ret < 0) + return ret; + } } return 0; @@ -350,6 +428,15 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) return ret; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = v4l2_async_register_subdev(subdev); + if (ret < 0) { + dev_err(csi->dev, + "failed to register subdev: %d\n", ret); + return ret; + } + } + return 0; } @@ -389,8 +476,12 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { subdev = &chan->subdev; - if (subdev->dev) + if (subdev->dev) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_unregister_subdev(subdev); media_entity_cleanup(&subdev->entity); + } + list_del(&chan->list); kfree(chan); } @@ -427,13 +518,14 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; - } + else + ret = tegra_csi_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate channels: %d\n", ret); + goto cleanup; } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 93bd2a0..78a5110 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -7,6 +7,7 @@ #define __TEGRA_CSI_H__ #include +#include #include /* diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3492a8a..253bf33 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -230,7 +230,7 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) tegra_channel_capture_setup(chan); /* recover CSI block */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_csi_subdev(chan); tegra_csi_error_recover(subdev); } diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 93edade..5e19bab 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) return container_of(vb, struct tegra_channel_buffer, buf); } +static inline struct tegra_vi_graph_entity * +to_tegra_vi_graph_entity(struct v4l2_async_subdev *asd) +{ + return container_of(asd, struct tegra_vi_graph_entity, asd); +} + static int tegra_get_format_idx_by_code(struct tegra_vi *vi, unsigned int code, unsigned int offset) @@ -146,28 +153,64 @@ static void tegra_channel_buffer_queue(struct vb2_buffer *vb) } struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) +tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan) +{ + struct media_pad *pad; + + pad = media_entity_remote_pad(&chan->pad); + if (!pad) + return NULL; + + return media_entity_to_v4l2_subdev(pad->entity); +} + +struct v4l2_subdev * +tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan) { struct media_pad *pad; struct v4l2_subdev *subdev; struct media_entity *entity; - pad = media_entity_remote_pad(&chan->pad); - entity = pad->entity; - subdev = media_entity_to_v4l2_subdev(entity); + subdev = tegra_channel_get_remote_csi_subdev(chan); + if (!subdev) + return NULL; + + pad = &subdev->entity.pads[0]; + while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) { + pad = media_entity_remote_pad(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + entity = pad->entity; + pad = &entity->pads[0]; + subdev = media_entity_to_v4l2_subdev(entity); + } return subdev; } int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { - struct v4l2_subdev *subdev; + struct v4l2_subdev *subdev, *csi_subdev, *src_subdev; int ret; - /* stream CSI */ - subdev = tegra_channel_get_remote_subdev(chan); + csi_subdev = tegra_channel_get_remote_csi_subdev(chan); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + /* + * Tegra CSI receiver can detect the first LP to HS transition. + * So, start the CSI stream-on prior to sensor stream-on and + * vice-versa for stream-off. + */ + subdev = on ? csi_subdev : src_subdev; ret = v4l2_subdev_call(subdev, video, s_stream, on); - if (on && ret < 0 && ret != -ENOIOCTLCMD) + if (ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + subdev = on ? src_subdev : csi_subdev; + ret = v4l2_subdev_call(subdev, video, s_stream, on); + if (ret < 0 && ret != -ENOIOCTLCMD) return ret; return 0; @@ -252,7 +295,7 @@ static int tegra_channel_g_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); return v4l2_g_parm_cap(&chan->video, subdev, a); } @@ -262,7 +305,7 @@ static int tegra_channel_s_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); return v4l2_s_parm_cap(&chan->video, subdev, a); } @@ -284,7 +327,7 @@ static int tegra_channel_enum_framesizes(struct file *file, void *fh, fse.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); ret = v4l2_subdev_call(subdev, pad, enum_frame_size, NULL, &fse); if (ret) return ret; @@ -316,7 +359,7 @@ static int tegra_channel_enum_frameintervals(struct file *file, void *fh, fie.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_source_subdev(chan); ret = v4l2_subdev_call(subdev, pad, enum_frame_interval, NULL, &fie); if (ret) return ret; @@ -335,6 +378,9 @@ static int tegra_channel_enum_format(struct file *file, void *fh, unsigned int index = 0, i; unsigned long *fmts_bitmap = chan->tpg_fmts_bitmap; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + fmts_bitmap = chan->fmts_bitmap; + if (f->index >= bitmap_weight(fmts_bitmap, MAX_FORMAT_NUM)) return -EINVAL; @@ -391,8 +437,12 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + int ret; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!subdev) + return -ENODEV; - subdev = tegra_channel_get_remote_subdev(chan); pad_cfg = v4l2_subdev_alloc_pad_config(subdev); if (!pad_cfg) return -ENOMEM; @@ -412,7 +462,10 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -452,8 +505,11 @@ static int tegra_channel_set_format(struct file *file, void *fh, fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - subdev = tegra_channel_get_remote_subdev(chan); - v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + subdev = tegra_channel_get_remote_source_subdev(chan); + ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -463,15 +519,50 @@ static int tegra_channel_set_format(struct file *file, void *fh, return 0; } +static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) +{ + int ret, index; + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + /* + * Initialize channel format to the sub-device active format if there + * is corresponding match in the Tegra supported video formats. + */ + subdev = tegra_channel_get_remote_source_subdev(chan); + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret) + return ret; + + index = tegra_get_format_idx_by_code(chan->vi, fmt.format.code, 0); + if (index < 0) + return -EINVAL; + + chan->fmtinfo = &chan->vi->soc->video_formats[index]; + v4l2_fill_pix_format(&chan->format, &fmt.format); + chan->format.pixelformat = chan->fmtinfo->fourcc; + chan->format.bytesperline = chan->format.width * chan->fmtinfo->bpp; + chan->format.sizeimage = chan->format.bytesperline * + chan->format.height; + tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + + return 0; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { - /* currently driver supports internal TPG only */ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + if (inp->index) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; - strscpy(inp->name, "Tegra TPG", sizeof(inp->name)); + subdev = tegra_channel_get_remote_source_subdev(chan); + strscpy(inp->name, subdev->name, sizeof(inp->name)); return 0; } @@ -578,6 +669,22 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#else + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!subdev) + return -ENODEV; + + ret = v4l2_ctrl_add_handler(&chan->ctrl_handler, subdev->ctrl_handler, + NULL, true); + if (ret < 0) { + dev_err(chan->vi->dev, + "failed to add subdev %s ctrl handler: %d\n", + subdev->name, ret); + v4l2_ctrl_handler_free(&chan->ctrl_handler); + return ret; + } #endif /* setup the controls */ @@ -608,6 +715,61 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_set(chan->tpg_fmts_bitmap, index, 1); } +static int vi_fmts_bitmap_init(struct tegra_vi_channel *chan) +{ + int index, ret, match_code = 0; + struct v4l2_subdev *subdev; + struct v4l2_subdev_mbus_code_enum code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM); + + /* + * Set the bitmap bits based on all the matched formats between the + * available media bus formats of sub-device and the pre-defined Tegra + * supported video formats. + */ + subdev = tegra_channel_get_remote_source_subdev(chan); + while (1) { + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code, + NULL, &code); + if (ret < 0) + break; + + index = tegra_get_format_idx_by_code(chan->vi, code.code, 0); + while (index >= 0) { + bitmap_set(chan->fmts_bitmap, index, 1); + if (!match_code) + match_code = code.code; + /* look for other formats with same mbus code */ + index = tegra_get_format_idx_by_code(chan->vi, + code.code, + index + 1); + } + + code.index++; + } + + /* + * Set the bitmap bit corresponding to default tegra video format if + * there are no matched formats. + */ + if (!match_code) { + match_code = tegra_default_format.code; + index = tegra_get_format_idx_by_code(chan->vi, match_code, 0); + if (WARN_ON(index < 0)) + return -EINVAL; + + bitmap_set(chan->fmts_bitmap, index, 1); + } + + /* initialize channel format to the sub-device active format */ + tegra_channel_set_subdev_active_fmt(chan); + + return 0; +} + static void tegra_channel_cleanup(struct tegra_vi_channel *chan) { v4l2_ctrl_handler_free(&chan->ctrl_handler); @@ -720,6 +882,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) goto free_v4l2_ctrl_hdl; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_notifier_init(&chan->notifier); + return 0; free_v4l2_ctrl_hdl: @@ -733,28 +898,84 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) return ret; } -static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, + struct device_node *node) { struct tegra_vi_channel *chan; + + /* + * Do not use devm_kzalloc as memory is freed immediately + * when device instance is unbound but application might still + * be holding the device node open. Channel memory allocated + * with kzalloc is freed during video device release callback. + */ + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->vi = vi; + chan->portno = port_num; + chan->of_node = node; + list_add_tail(&chan->list, &vi->vi_chans); + + return 0; +} + +static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +{ unsigned int port_num; unsigned int nchannels = vi->soc->vi_max_channels; + int ret; for (port_num = 0; port_num < nchannels; port_num++) { - /* - * Do not use devm_kzalloc as memory is freed immediately - * when device instance is unbound but application might still - * be holding the device node open. Channel memory allocated - * with kzalloc is freed during video device release callback. - */ - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; + ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_vi_channels_alloc(struct tegra_vi *vi) +{ + struct device_node *node = vi->dev->of_node; + struct device_node *ep = NULL; + struct device_node *ports; + struct device_node *port; + unsigned int port_num; + int ret; + + ports = of_get_child_by_name(node, "ports"); + if (!ports) + return -ENODEV; + + for_each_child_of_node(ports, port) { + if (!of_node_name_eq(port, "port")) + continue; + + ret = of_property_read_u32(port, "reg", &port_num); + if (ret < 0) + continue; + + if (port_num > vi->soc->vi_max_channels) { + of_node_put(ports); + dev_err(vi->dev, "invalid port num %d\n", port_num); + return -EINVAL; + } - chan->vi = vi; - chan->portno = port_num; - list_add_tail(&chan->list, &vi->vi_chans); + ep = of_get_child_by_name(port, "endpoint"); + if (!ep) + continue; + + of_node_put(ep); + ret = tegra_vi_channel_alloc(vi, port_num, port); + if (ret < 0) { + of_node_put(ports); + return ret; + } } + of_node_put(ports); return 0; } @@ -905,6 +1126,347 @@ static int __maybe_unused vi_runtime_suspend(struct device *dev) return 0; } +/* + * Graph Management + */ +static struct tegra_vi_graph_entity * +tegra_vi_graph_find_entity(struct tegra_vi_channel *chan, + const struct fwnode_handle *fwnode) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + if (entity->asd.match.fwnode == fwnode) + return entity; + } + + return NULL; +} + +static int tegra_vi_graph_build(struct tegra_vi_channel *chan, + struct tegra_vi_graph_entity *entity) +{ + struct tegra_vi *vi = chan->vi; + struct tegra_vi_graph_entity *ent; + struct fwnode_handle *ep = NULL; + struct v4l2_fwnode_link link; + struct media_entity *local = entity->entity; + struct media_entity *remote; + struct media_pad *local_pad; + struct media_pad *remote_pad; + u32 link_flags = MEDIA_LNK_FL_ENABLED; + int ret = 0; + + dev_dbg(vi->dev, "creating links for entity %s\n", local->name); + + while (1) { + ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode, + ep); + if (!ep) + break; + + ret = v4l2_fwnode_parse_link(ep, &link); + if (ret < 0) { + dev_err(vi->dev, "failed to parse link for %pOF: %d\n", + to_of_node(ep), ret); + continue; + } + + if (link.local_port >= local->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.local_port, to_of_node(link.local_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + local_pad = &local->pads[link.local_port]; + /* Remote node is vi node. So use channel video entity and pad + * as remote/sink. + */ + if (link.remote_node == of_fwnode_handle(vi->dev->of_node)) { + remote = &chan->video.entity; + remote_pad = &chan->pad; + goto create_link; + } + + /* + * Skip sink ports, they will be processed from the other end + * of the link. + */ + if (local_pad->flags & MEDIA_PAD_FL_SINK) { + dev_dbg(vi->dev, "skipping sink port %pOF:%u\n", + to_of_node(link.local_node), link.local_port); + v4l2_fwnode_put_link(&link); + continue; + } + + /* find the remote entity from notifier list */ + ent = tegra_vi_graph_find_entity(chan, link.remote_node); + if (!ent) { + dev_err(vi->dev, "no entity found for %pOF\n", + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -ENODEV; + break; + } + + remote = ent->entity; + if (link.remote_port >= remote->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.remote_port, + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + remote_pad = &remote->pads[link.remote_port]; + +create_link: + dev_dbg(vi->dev, "creating %s:%u -> %s:%u link\n", + local->name, local_pad->index, + remote->name, remote_pad->index); + + ret = media_create_pad_link(local, local_pad->index, + remote, remote_pad->index, + link_flags); + v4l2_fwnode_put_link(&link); + if (ret < 0) { + dev_err(vi->dev, + "failed to create %s:%u -> %s:%u link: %d\n", + local->name, local_pad->index, + remote->name, remote_pad->index, ret); + break; + } + } + + fwnode_handle_put(ep); + return ret; +} + +static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + struct v4l2_subdev *subdev; + struct tegra_vi_channel *chan; + struct tegra_vi *vi; + int ret; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + dev_dbg(vi->dev, "notify complete, all subdevs registered\n"); + + /* + * Video device node should be created at the end of all the device + * related initialization/setup. + * Current video_register_device() does both initialize and register + * video device in same API. + * + * TODO: Update v4l2-dev driver to split initialize and register into + * separate APIs and then update Tegra video driver to do video device + * initialize followed by all video device related setup and then + * register the video device. + */ + ret = video_register_device(&chan->video, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + dev_err(vi->dev, + "failed to register video device: %d\n", ret); + goto unregister_video; + } + + /* create links between the entities */ + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + ret = tegra_vi_graph_build(chan, entity); + if (ret < 0) + goto unregister_video; + } + + ret = tegra_channel_setup_ctrl_handler(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to setup channel controls: %d\n", ret); + goto unregister_video; + } + + ret = vi_fmts_bitmap_init(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to initialize formats bitmap: %d\n", ret); + goto unregister_video; + } + + subdev = tegra_channel_get_remote_csi_subdev(chan); + if (!subdev) { + ret = -ENODEV; + dev_err(vi->dev, + "failed to get remote csi subdev: %d\n", ret); + goto unregister_video; + } + + v4l2_set_subdev_hostdata(subdev, chan); + + return 0; + +unregister_video: + video_unregister_device(&chan->video); + return ret; +} + +static int tegra_vi_graph_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + /* + * Locate the entity corresponding to the bound subdev and store the + * subdev pointer. + */ + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (!entity) { + dev_err(vi->dev, "no entity for subdev %s\n", subdev->name); + return -EINVAL; + } + + if (entity->subdev) { + dev_err(vi->dev, "duplicate subdev for node %pOF\n", + to_of_node(entity->asd.match.fwnode)); + return -EINVAL; + } + + dev_dbg(vi->dev, "subdev %s bound\n", subdev->name); + entity->entity = &subdev->entity; + entity->subdev = subdev; + + return 0; +} + +static const struct v4l2_async_notifier_operations tegra_vi_async_ops = { + .bound = tegra_vi_graph_notify_bound, + .complete = tegra_vi_graph_notify_complete, +}; + +static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, + struct fwnode_handle *fwnode) +{ + struct tegra_vi *vi = chan->vi; + struct fwnode_handle *ep = NULL; + struct fwnode_handle *remote = NULL; + struct v4l2_async_subdev *asd; + struct device_node *node = NULL; + int ret; + + dev_dbg(vi->dev, "parsing node %pOF\n", to_of_node(fwnode)); + + /* parse all the remote entities and put them into the list */ + for_each_endpoint_of_node(to_of_node(fwnode), node) { + ep = of_fwnode_handle(node); + remote = fwnode_graph_get_remote_port_parent(ep); + if (!remote) { + dev_err(vi->dev, + "remote device at %pOF not found\n", node); + ret = -EINVAL; + goto cleanup; + } + + /* skip entities that are already processed */ + if (remote == dev_fwnode(vi->dev) || + tegra_vi_graph_find_entity(chan, remote)) { + fwnode_handle_put(remote); + continue; + } + + asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, + remote, sizeof(struct tegra_vi_graph_entity)); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + dev_err(vi->dev, + "failed to add subdev to notifier: %d\n", ret); + fwnode_handle_put(remote); + goto cleanup; + } + + ret = tegra_vi_graph_parse_one(chan, remote); + if (ret < 0) { + fwnode_handle_put(remote); + goto cleanup; + } + + fwnode_handle_put(remote); + } + + return 0; + +cleanup: + dev_err(vi->dev, "failed parsing the graph: %d\n", ret); + v4l2_async_notifier_cleanup(&chan->notifier); + of_node_put(node); + return ret; +} + +static int tegra_vi_graph_init(struct tegra_vi *vi) +{ + struct tegra_video_device *vid = dev_get_drvdata(vi->client.host); + struct tegra_vi_channel *chan; + struct fwnode_handle *fwnode = dev_fwnode(vi->dev); + int ret; + struct fwnode_handle *remote = NULL; + + /* + * Walk the links to parse the full graph. Each channel will have + * one endpoint of the composite node. Start by parsing the + * composite node and parse the remote entities in turn. + * Each channel will register v4l2 async notifier to make the graph + * independent between the channels so we can the current channel + * in case of something wrong during graph parsing and continue with + * next channels. + */ + list_for_each_entry(chan, &vi->vi_chans, list) { + remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0); + if (!remote) + continue; + + ret = tegra_vi_graph_parse_one(chan, remote); + fwnode_handle_put(remote); + if (ret < 0 || list_empty(&chan->notifier.asd_list)) + continue; + + chan->notifier.ops = &tegra_vi_async_ops; + ret = v4l2_async_notifier_register(&vid->v4l2_dev, + &chan->notifier); + if (ret < 0) { + dev_err(vi->dev, + "failed to register channel %d notifier: %d\n", + chan->portno, ret); + v4l2_async_notifier_cleanup(&chan->notifier); + } + } + + return 0; +} + +static void tegra_vi_graph_cleanup(struct tegra_vi *vi) +{ + struct tegra_vi_channel *chan; + + list_for_each_entry(chan, &vi->vi_chans, list) { + vb2_video_unregister_device(&chan->video); + v4l2_async_notifier_unregister(&chan->notifier); + v4l2_async_notifier_cleanup(&chan->notifier); + } +} + static int tegra_vi_init(struct host1x_client *client) { struct tegra_video_device *vid = dev_get_drvdata(client->host); @@ -918,13 +1480,14 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto free_chans; - } + else + ret = tegra_vi_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate vi channels: %d\n", ret); + goto free_chans; } ret = tegra_vi_channels_init(vi); @@ -933,6 +1496,12 @@ static int tegra_vi_init(struct host1x_client *client) vid->vi = vi; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_graph_init(vi); + if (ret < 0) + goto free_chans; + } + return 0; free_chans: @@ -946,6 +1515,8 @@ static int tegra_vi_init(struct host1x_client *client) static int tegra_vi_exit(struct host1x_client *client) { + struct tegra_vi *vi = host1x_client_to_vi(client); + /* * Do not cleanup the channels here as application might still be * holding video device nodes. Channels cleanup will happen during @@ -953,6 +1524,9 @@ static int tegra_vi_exit(struct host1x_client *client) * device nodes are released. */ + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_vi_graph_cleanup(vi); + return 0; } diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index 6272c9a..7d6b7a6 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,19 @@ struct tegra_vi { }; /** + * struct tegra_vi_graph_entity - Entity in the video graph + * + * @asd: subdev asynchronous registration information + * @entity: media entity from the corresponding V4L2 subdev + * @subdev: V4L2 subdev + */ +struct tegra_vi_graph_entity { + struct v4l2_async_subdev asd; + struct media_entity *entity; + struct v4l2_subdev *subdev; +}; + +/** * struct tegra_vi_channel - Tegra video channel * * @list: list head for this entry @@ -138,10 +152,13 @@ struct tegra_vi { * @done_lock: protects the capture done queue list * * @portno: VI channel port number + * @of_node: device node of VI channel * * @ctrl_handler: V4L2 control handler of this video channel + * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats * @tpg_fmts_bitmap: a bitmap for supported TPG formats * @pg_mode: test pattern generator mode (disabled/direct/patch) + * @notifier: V4L2 asynchronous subdevs notifier */ struct tegra_vi_channel { struct list_head list; @@ -174,10 +191,14 @@ struct tegra_vi_channel { spinlock_t done_lock; unsigned char portno; + struct device_node *of_node; struct v4l2_ctrl_handler ctrl_handler; + DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); enum tegra_vi_pg_mode pg_mode; + + struct v4l2_async_notifier notifier; }; /** @@ -249,7 +270,9 @@ extern const struct tegra_vi_soc tegra210_vi_soc; #endif struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan); +tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); +struct v4l2_subdev * +tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); void tegra_channel_release_buffers(struct tegra_vi_channel *chan, enum vb2_buffer_state state); From patchwork Wed Jul 15 04:20:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65481 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYob-00Fbmg-Sf; Wed, 15 Jul 2020 04:14:45 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728448AbgGOETi (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:38 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4631 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728402AbgGOETh (ORCPT ); Wed, 15 Jul 2020 00:19:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:37 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:37 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:36 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:36 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 13/18] media: tegra-video: Add support for selection ioctl ops Date: Tue, 14 Jul 2020 21:20:50 -0700 Message-ID: <1594786855-26506-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786764; bh=vbR9FAjVS0THVLK754Oo3pfDyx/oljFrBthHzWq+SxM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=QodDpyNL0etP9O5dHLjgvXjdvl856eDs1N/wzqFh1vE2IBqy8jxC06iH+p2JRVhfi A58bA05S9SG8v8Op7pkTUJz7Idxdf6K5pfx7jQGof52gpmjiq67rnUd/OTUwJwJ/Tm 9FHFgjvGKGBg3RQlA9MIC+U/7fq80xDsIjr6moLNvT97KLxSbKirTrlVkOSuxefMin rKXwz66kLU/DDW6ahIyJqiF97fN5gAEwCCiUnAL14w7ehuwXvLvPHYq5yS5UPN0+DV 3qGxQX2nkpLxjXSRslRIQkdXbD3cPSTrQi/iZ4qQL3jBP1T+Y0eWpMWty/cPR5dPQo 2v8N223fI9uKg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds selection v4l2 ioctl operations to allow configuring a selection rectangle in the sensor through the Tegra video device node. Some sensor drivers supporting crop uses try_crop rectangle from v4l2_subdev_pad_config during try format for computing binning. So with selection ops support, this patch also updates try format to use try crop rectangle either from subdev frame size enumeration or from subdev crop boundary. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 5e19bab..676e24e2 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -437,6 +437,13 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + struct v4l2_subdev_frame_size_enum fse = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = V4L2_SEL_TGT_CROP_BOUNDS, + }; int ret; subdev = tegra_channel_get_remote_source_subdev(chan); @@ -462,6 +469,24 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); + + /* + * Attempt to obtain the format size from subdev. + * If not available, try to get crop boundary from subdev. + */ + fse.code = fmtinfo->code; + ret = v4l2_subdev_call(subdev, pad, enum_frame_size, pad_cfg, &fse); + if (ret) { + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (ret) + return -EINVAL; + pad_cfg->try_crop.width = sdsel.r.width; + pad_cfg->try_crop.height = sdsel.r.height; + } else { + pad_cfg->try_crop.width = fse.max_width; + pad_cfg->try_crop.height = fse.max_height; + } + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); if (ret < 0) return ret; @@ -551,6 +576,85 @@ static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) return 0; } +static int tegra_channel_g_selection(struct file *file, void *priv, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + }; + int ret; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, get_selection)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + /* + * Try the get selection operation and fallback to get format if not + * implemented. + */ + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (!ret) + sel->r = sdsel.r; + if (ret != -ENOIOCTLCMD) + return ret; + + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret < 0) + return ret; + + sel->r.left = 0; + sel->r.top = 0; + sel->r.width = fmt.format.width; + sel->r.height = fmt.format.height; + + return 0; +} + +static int tegra_channel_s_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + int ret; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + .flags = sel->flags, + .r = sel->r, + }; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, set_selection)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vb2_is_busy(&chan->queue)) + return -EBUSY; + + ret = v4l2_subdev_call(subdev, pad, set_selection, NULL, &sdsel); + if (!ret) { + sel->r = sdsel.r; + /* + * Subdev active format resolution may have changed during + * set selection operation. So, update channel format to + * the sub-device active format. + */ + return tegra_channel_set_subdev_active_fmt(chan); + } + + return ret; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { @@ -608,6 +712,8 @@ static const struct v4l2_ioctl_ops tegra_channel_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_g_selection = tegra_channel_g_selection, + .vidioc_s_selection = tegra_channel_s_selection, }; /* From patchwork Wed Jul 15 04:20:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65482 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYof-00Fbmg-Lg; Wed, 15 Jul 2020 04:14:46 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728496AbgGOETk (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:40 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11997 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728421AbgGOETi (ORCPT ); Wed, 15 Jul 2020 00:19:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:18:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:38 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:38 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:37 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:37 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:37 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 14/18] gpu: host1x: mipi: Update tegra_mipi_request() to be node based Date: Tue, 14 Jul 2020 21:20:51 -0700 Message-ID: <1594786855-26506-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786720; bh=DBvHcZ7/o4zFdY0BE62wZHO/OZDDaWxvCBsDSvvgBwM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lsT829TnseJglcetzgZABqP7FV3TJXEV+S75w/z3n1mV+bQdwx759HX11ivkcWNTZ 62WaaxRbpX3yOqjgTxDY0ADlcldBsdCHGK+PMiAV7p7pdb3wbqJHoG6f9bnp91dU31 jfwIIC+bpnMwIjUBj+QULK4wSGWoPnco7cwjS6OeUZj7HuY8+/WZBATNmwVoxnbIqq ZclP2XUpx8KlAj9FTKNffvTvSq8yeKHnxJo5m9NL32eqX1k4XIeqyTm0SZtN7d6hTY 2tAkdShL4D3xvUoE11Fn3PCCfeOfnEyvFM6j38nAKF36eFf4WQ3g9jM7GH4C6RMtIS tgnS6m1Sx1/7w== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra CSI driver need a separate MIPI device for each channel as calibration of corresponding MIPI pads for each channel should happen independently. So, this patch updates tegra_mipi_request() API to add a device_node pointer argument to allow creating mipi device for specific device node rather than a device. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dsi.c | 2 +- drivers/gpu/host1x/mipi.c | 4 ++-- include/linux/host1x.h | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 38beab9..3c09e29 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -1618,7 +1618,7 @@ static int tegra_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->regs)) return PTR_ERR(dsi->regs); - dsi->mipi = tegra_mipi_request(&pdev->dev); + dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); if (IS_ERR(dsi->mipi)) return PTR_ERR(dsi->mipi); diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e00809d..762d349 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -206,9 +206,9 @@ static int tegra_mipi_power_down(struct tegra_mipi *mipi) return 0; } -struct tegra_mipi_device *tegra_mipi_request(struct device *device) +struct tegra_mipi_device *tegra_mipi_request(struct device *device, + struct device_node *np) { - struct device_node *np = device->of_node; struct tegra_mipi_device *dev; struct of_phandle_args args; int err; diff --git a/include/linux/host1x.h b/include/linux/host1x.h index a3a568b..9e67841 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -328,7 +328,8 @@ int host1x_client_resume(struct host1x_client *client); struct tegra_mipi_device; -struct tegra_mipi_device *tegra_mipi_request(struct device *device); +struct tegra_mipi_device *tegra_mipi_request(struct device *device, + struct device_node *np); void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); From patchwork Wed Jul 15 04:20:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65486 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYp8-00Fbnw-PD; Wed, 15 Jul 2020 04:15:15 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728806AbgGOEUI (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:08 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9602 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728478AbgGOETk (ORCPT ); Wed, 15 Jul 2020 00:19:40 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:46 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:39 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:39 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:39 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:39 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:38 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 15/18] gpu: host1x: mipi: Use readl_relaxed_poll_timeout in tegra_mipi_wait Date: Tue, 14 Jul 2020 21:20:52 -0700 Message-ID: <1594786855-26506-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786666; bh=OrA56lLocgK9NzCJgW1OH13QXVaE/JCoai+p9SudmJM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EagUyXsE4GMVuPsntbJiXG3xrszqGUU+vvJPtKF6z8xFdQbeMP6YtaTGIfslblg9g Ay6PkUk5h9UcorGLN7CwC6ccJ+8VofSHlRiew9ls9mHV0W/+c1mskBQZNZNE0fbZxV /bdIPL/o2MgnZRXPNO2sSrS9av/ebTn57GlcySbqWNHOAyhAWq6BnTXc1PXRIRlgDw lJoNHGNnd6atAPF2x/4cxdAmXFq+nIoQDqy5SJjJrhMa28p5t2y2Uoce8bZh94s1PR Lg7hDeBcXBkEmOvqY4xMbVcMBoOhVH7wWWfVpMFJjy2q3CeMB4/gT7x9mTirjIl/O4 ztHF1t/jb7OWA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Use readl_relaxed_poll_timeout() in tegra_mipi_wait() to simplify the code. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/host1x/mipi.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index 762d349..259e70c 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -21,9 +21,9 @@ */ #include -#include #include #include +#include #include #include #include @@ -295,19 +295,15 @@ EXPORT_SYMBOL(tegra_mipi_disable); static int tegra_mipi_wait(struct tegra_mipi *mipi) { - unsigned long timeout = jiffies + msecs_to_jiffies(250); + void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2); u32 value; + int err; - while (time_before(jiffies, timeout)) { - value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); - if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && - (value & MIPI_CAL_STATUS_DONE) != 0) - return 0; - - usleep_range(10, 50); - } - - return -ETIMEDOUT; + err = readl_relaxed_poll_timeout(status_reg, value, + !(value & MIPI_CAL_STATUS_ACTIVE) && + (value & MIPI_CAL_STATUS_DONE), 50, + 250000); + return err; } int tegra_mipi_calibrate(struct tegra_mipi_device *device) From patchwork Wed Jul 15 04:20:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65485 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYp3-00Fbnk-46; Wed, 15 Jul 2020 04:15:09 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728788AbgGOEUD (ORCPT + 1 other); Wed, 15 Jul 2020 00:20:03 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9609 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728518AbgGOETl (ORCPT ); Wed, 15 Jul 2020 00:19:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:17:47 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Jul 2020 21:19:40 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:40 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:39 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait Date: Tue, 14 Jul 2020 21:20:53 -0700 Message-ID: <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786667; bh=tqa8cFH9kC/IhmkUPxcaINoqX9Dl2lsTo66zcOpzXBA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WKGDFFwkS7eTYdWRlwFfwL6yY8dpiYSCcy7k8J/thmZGgtRvBxPWPI+Hg+haKyrMH FRZJ4iOR6szK6WvZqcW9gUam8bqjRz704ODJop3nwnnjtbpkSWlxD4kaGJt/8mzDiV eqmyPEWhts0zP083fZ47kW1qnabVqFVPnnFFYMw/62iEeq1yvYRErftXFKkLMAT1Oh wADmo5U7pE7pts8W9/Fsnd1HsSrrkxF9kkd56sEPbl/aGvtJbOZ2urvVOt9f/TKFkM Yjo95p4TQaGT5C1b38EmvabMxXzcemjKOgeK+iJoJ0MHhCg7ApWQT/3G6VHVGLBYii oz+Ai+bjVsTYg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no SW can trigger MIPI pads calibration any time after power on but calibration results will be latched and applied to the pads by MIPI CAL unit only when the link is in LP-11 state and then status register will be updated. For CSI, trigger of pads calibration happen during CSI stream enable where CSI receiver is kept ready prior to sensor or CSI transmitter stream start. So, pads may not be in LP-11 at this time and waiting for the calibration to be done immediate after calibration start will result in timeout. This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() so triggering for calibration and waiting for it to complete can happen at different stages. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/drm/tegra/dsi.c | 7 ++++++- drivers/gpu/host1x/mipi.c | 17 +++++++++++++---- include/linux/host1x.h | 1 + 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 3c09e29..1a76f1f 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -670,6 +670,7 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { u32 value; + int ret; /* * XXX Is this still needed? The module reset is deasserted right @@ -693,7 +694,11 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - return tegra_mipi_calibrate(dsi->mipi); + ret = tegra_mipi_calibrate(dsi->mipi); + if (ret < 0) + return ret; + + return tegra_mipi_wait(dsi->mipi); } static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index 259e70c..e606464 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -293,18 +293,29 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) } EXPORT_SYMBOL(tegra_mipi_disable); -static int tegra_mipi_wait(struct tegra_mipi *mipi) +int tegra_mipi_wait(struct tegra_mipi_device *device) { + struct tegra_mipi *mipi = device->mipi; void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2); u32 value; int err; + err = clk_enable(device->mipi->clk); + if (err < 0) + return err; + + mutex_lock(&device->mipi->lock); + err = readl_relaxed_poll_timeout(status_reg, value, !(value & MIPI_CAL_STATUS_ACTIVE) && (value & MIPI_CAL_STATUS_DONE), 50, 250000); + mutex_unlock(&device->mipi->lock); + clk_disable(device->mipi->clk); + return err; } +EXPORT_SYMBOL(tegra_mipi_wait); int tegra_mipi_calibrate(struct tegra_mipi_device *device) { @@ -370,12 +381,10 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) value |= MIPI_CAL_CTRL_START; tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); - err = tegra_mipi_wait(device->mipi); - mutex_unlock(&device->mipi->lock); clk_disable(device->mipi->clk); - return err; + return 0; } EXPORT_SYMBOL(tegra_mipi_calibrate); diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 9e67841..20c885d 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -334,5 +334,6 @@ void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); int tegra_mipi_calibrate(struct tegra_mipi_device *device); +int tegra_mipi_wait(struct tegra_mipi_device *device); #endif From patchwork Wed Jul 15 04:20:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65483 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYop-00FbnA-Jm; Wed, 15 Jul 2020 04:14:56 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728571AbgGOETm (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:42 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4642 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728532AbgGOETm (ORCPT ); Wed, 15 Jul 2020 00:19:42 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:19:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:41 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:41 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:41 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:41 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:40 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 17/18] media: tegra-video: Add CSI MIPI pads calibration Date: Tue, 14 Jul 2020 21:20:54 -0700 Message-ID: <1594786855-26506-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786769; bh=Ah9VTi1AABBsKQfXAi49KcBbZ1sPcfnwuIUbjiM3nVs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ei3KOiqBwd54qMK+GrKDSAPG06t7zT4OpORFtI6uqbIshnRups7TcalnaTsA0eNLE seg7CRJXcH+ALtH9XEJFWyau97q6q0pZCXaK2yfZNtdQpL2YhF9VPEHaCq17zCgkJA zCvx9WXvOaMYcdO4ghDaZhH0WZ+IDs4eh6lrGBiGJJJJ4KqH1UvnVRj8NU5aDSWVu9 66dkHAkj45m1vC0eI3s75Kt1GbBkiTBYLHHK48YJZ/J57njX0YgsYz7OnP51gHLIUb bN+DsIIxxbkwNAoa8SLm53bSBjV7GhLx4GDEzwg7TIZMNsPxnI7EIXY+poodOb7X9V nENCv46zVApmw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no CSI MIPI pads need to be enabled and calibrated for capturing from the external sensor or transmitter. MIPI CAL unit calibrates MIPI pads pull-up, pull-down and termination impedances. Calibration is done by co-work of MIPI BIAS pad and MIPI CAL control unit. Triggering calibration start can happen any time after MIPI pads are enabled but calibration results will be latched and applied to MIPI pads by MIPI CAL unit only when the link is in LP11 state and then calibration status register gets updated. This patch enables CSI MIPI pads and calibrates them during streaming. Tegra CSI receiver is able to catch the very first clock transition. So, CSI receiver is always enabled prior to sensor streaming and trigger of calibration start is done during CSI subdev streaming and status of calibration is verified after sensor stream on. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 44 +++++++++++++++++++++++++++++++-- drivers/staging/media/tegra-video/csi.h | 2 ++ drivers/staging/media/tegra-video/vi.c | 16 ++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index c21dd09..75c844d 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -252,15 +252,42 @@ static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) return ret; } + if (csi_chan->mipi) { + ret = tegra_mipi_enable(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to enable MIPI pads: %d\n", + ret); + goto rpm_put; + } + + /* + * CSI MIPI pads PULLUP, PULLDN and TERM impedances + * need to be calibrated after power on. + * So, trigger the calibration start here and results + * will be latched and applied to the pads when link is + * in LP11 state during start of sensor streaming. + */ + tegra_mipi_calibrate(csi_chan->mipi); + } + ret = csi->ops->csi_start_streaming(csi_chan); if (ret < 0) - goto rpm_put; + goto disable_mipi; return 0; } csi->ops->csi_stop_streaming(csi_chan); +disable_mipi: + if (csi_chan->mipi) { + ret = tegra_mipi_disable(csi_chan->mipi); + if (ret < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", ret); + } + rpm_put: pm_runtime_put(csi->dev); return ret; @@ -294,6 +321,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; + int ret = 0; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -312,7 +340,16 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; } - return 0; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + chan->mipi = tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret = PTR_ERR(chan->mipi); + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } + + return ret; } static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) @@ -475,6 +512,9 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) struct tegra_csi_channel *chan, *tmp; list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { + if (chan->mipi) + tegra_mipi_free(chan->mipi); + subdev = &chan->subdev; if (subdev->dev) { if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 78a5110..0d50fc3 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -50,6 +50,7 @@ struct tegra_csi; * @framerate: active framerate for TPG * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format + * @mipi: mipi device for corresponding csi channel pads */ struct tegra_csi_channel { struct list_head list; @@ -65,6 +66,7 @@ struct tegra_csi_channel { unsigned int framerate; unsigned int h_blank; unsigned int v_blank; + struct tegra_mipi_device *mipi; }; /** diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 676e24e2..58ad992 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -191,6 +191,7 @@ tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan) int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { struct v4l2_subdev *subdev, *csi_subdev, *src_subdev; + struct tegra_csi_channel *csi_chan; int ret; csi_subdev = tegra_channel_get_remote_csi_subdev(chan); @@ -213,6 +214,21 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) if (ret < 0 && ret != -ENOIOCTLCMD) return ret; + /* + * CSI subdev stream-on triggers start of MIPI pads calibration. + * Calibration results are latched and applied to the pads when + * link is in LP11 state which will happen during sensor stream-on. + * So, wait for pads calibration to complete here. + */ + csi_chan = v4l2_get_subdevdata(csi_subdev); + if (on && csi_chan->mipi) { + ret = tegra_mipi_wait(csi_chan->mipi); + if (ret < 0) + dev_err(csi_chan->csi->dev, + "MIPI calibration failed: %d\n", ret); + return ret; + } + return 0; } From patchwork Wed Jul 15 04:20:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 65484 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jvYot-00FbnO-22; Wed, 15 Jul 2020 04:14:59 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728728AbgGOETx (ORCPT + 1 other); Wed, 15 Jul 2020 00:19:53 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:12018 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728606AbgGOETo (ORCPT ); Wed, 15 Jul 2020 00:19:44 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Jul 2020 21:18:45 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 14 Jul 2020 21:19:43 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 14 Jul 2020 21:19:43 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Jul 2020 04:19:42 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Jul 2020 04:19:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Jul 2020 21:19:42 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v3 18/18] media: tegra-video: Compute settle times based on the clock rate Date: Tue, 14 Jul 2020 21:20:55 -0700 Message-ID: <1594786855-26506-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594786725; bh=4rppkIezC/fsfilzoE7eu50OmLt8l8SIUvmDoxYu1fY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=RkKwnERV5Pt/Vp6Ucdpuot4TL9kaUx9tGgUSV81hitGIahzt8yvR/j2YstATPLwzr yhb5BOUHVM2Iv4/5m81tHB+zqbp0iGGXFVAVG9xWmaVNtB7EqqazCvpAYhZTXbEOaJ jBjM5bnJiBxAxFMDWnlzvvcEkg9TBNcNcZI1x+vBBpl652jjms3iivP/P6tkq5x4Yj NoANy1FB9et7ISiciizD1aG/mrguMD+I4PxnlCPHdjMIPAVcQd9CAkTaMVA99UbQIw +sKyr1ZAo3GcI8yzRWWLByeDGgsrWPTPi4iRIAcZc77FXanJpFesd69dmBx/mPtGKP x/vbS+in82A8Q== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Settle time determines the number of cil clock cyles to wait after LP00 when moving from LP to HS. This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil clock rate and pixel rate from the sensor and programs them during streaming. T-CLK-SETTLE time is the interval during which receiver will ignore any HS transitions on clock lane starting from the beginning of T-CLK-PREPARE. T-HS-SETTLE time is the interval during which recevier will ignore any HS transitions on data lane starting from the beginning of T-HS-PREPARE. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 55 ++++++++++++++++++++++++++++ drivers/staging/media/tegra-video/csi.h | 5 +++ drivers/staging/media/tegra-video/tegra210.c | 17 ++++++++- 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 75c844d..d9f9e3c 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -19,6 +19,8 @@ #include "csi.h" #include "video.h" +#define MHZ 1000000 + static inline struct tegra_csi * host1x_client_to_csi(struct host1x_client *client) { @@ -235,6 +237,59 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } +static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) +{ + struct tegra_vi_channel *chan; + struct v4l2_subdev *src_subdev; + struct v4l2_ctrl *ctrl; + + chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); + if (ctrl) + return v4l2_ctrl_g_ctrl_int64(ctrl); + + return 0; +} + +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time) +{ + struct tegra_csi *csi = csi_chan->csi; + unsigned int cil_clk_mhz; + unsigned int pix_clk_mhz; + int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + + cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; + pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; + + /* + * CLK Settle time is the interval during which HS receiver should + * ignore any clock lane HS transitions, starting from the beginning + * of T-CLK-PREPARE. + * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns + * + * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns + * midpoint = 197.5 ns + */ + *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; + + /* + * THS Settle time is the interval during which HS receiver should + * ignore any data lane HS transitions, starting from the beginning + * of THS-PREPARE. + * + * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI + * and 145ns+10UI. + * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI + * midpoint = 115ns + 8UI + */ + if (pix_clk_mhz) + *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz + / (2 * pix_clk_mhz) - 5000) / 1000; +} + static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 0d50fc3..c65ff73 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -51,6 +51,7 @@ struct tegra_csi; * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format * @mipi: mipi device for corresponding csi channel pads + * @pixel_rate: active pixel rate from the sensor on this channel */ struct tegra_csi_channel { struct list_head list; @@ -67,6 +68,7 @@ struct tegra_csi_channel { unsigned int h_blank; unsigned int v_blank; struct tegra_mipi_device *mipi; + unsigned int pixel_rate; }; /** @@ -147,4 +149,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; #endif void tegra_csi_error_recover(struct v4l2_subdev *subdev); +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 253bf33..ac066c0 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -7,6 +7,7 @@ * This source file contains Tegra210 supported video formats, * VI and CSI SoC specific data, operations and registers accessors. */ +#include #include #include #include @@ -98,6 +99,8 @@ #define BRICK_CLOCK_B_4X (0x2 << 16) #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 +#define CLK_SETTLE_MASK GENMASK(13, 8) +#define THS_SETTLE_MASK GENMASK(5, 0) #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c #define TEGRA_CSI_CIL_STATUS 0x010 #define TEGRA_CSI_CILX_STATUS 0x014 @@ -770,8 +773,14 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) { struct tegra_csi *csi = csi_chan->csi; unsigned int portno = csi_chan->csi_port_num; + u8 clk_settle_time = 0; + u8 ths_settle_time = 10; u32 val; + if (!csi_chan->pg_mode) + tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + &ths_settle_time); + csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); /* clean up status */ @@ -782,7 +791,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) /* CIL PHY registers setup */ cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); - cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); /* * The CSI unit provides for connection of up to six cameras in @@ -801,7 +812,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) BRICK_CLOCK_A_4X); cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); - cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); } else {