From patchwork Wed Jun 10 06:02:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64415 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitnM-006pBA-Oj; Wed, 10 Jun 2020 06:01:05 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726570AbgFJGE7 (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:59 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6065 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726078AbgFJGCp (ORCPT ); Wed, 10 Jun 2020 02:02:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:44 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:44 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:44 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:44 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 01/18] dt-bindings: i2c: tegra: Document Tegra210 VI I2C clocks and power-domains Date: Tue, 9 Jun 2020 23:02:23 -0700 Message-ID: <1591768960-31648-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768919; bh=IcdTxk/KfmzbsMYHUsUoDHLf4X+jjxTur+UzaaoB62c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IOF8V/dIjURU1Y7kRPqnexdrMWesOJc4m59hFwXd3q8zhRnTp+sL2rdz6P9sgZw/l v+qTOjHC9QRIk8ps8adfTZjvTnxUmZk1uQn+L7px3EAVb4yxuzX5D20An9CCJOdHaO vlVu/vU5NcE9J3drInaF7g59ABhLMa0DNf7m3ptGs57bKmQ1A8VqwPw34vxIzrFFxl kMFOEQzpk02tlsjZ3sDUcw7Q9hfozFM0RX2ZdNxesQd132ZUwnAJi/XdHkYn7fRt1T 0edxixeGJzbHFT98J8P2Kq3UZOhveRPvSseJBTMLFfE8WjoqBOHOkxGrSf4i5on7sG m3UhI6UiZIjMg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch documents missing clocks and power-domains of Tegra210 VI I2C. Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt index 18c0de3..3f2f990 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt @@ -35,12 +35,12 @@ Required properties: Due to above changes, Tegra114 I2C driver makes incompatible with previous hardware driver. Hence, tegra114 I2C controller is compatible with "nvidia,tegra114-i2c". - nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the - host1x domain and typically used for camera use-cases. This VI I2C - controller is mostly compatible with the programming model of the - regular I2C controllers with a few exceptions. The I2C registers start - at an offset of 0xc00 (instead of 0), registers are 16 bytes apart - (rather than 4) and the controller does not support slave mode. + nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus + and is part of VE power domain and typically used for camera use-cases. + This VI I2C controller is mostly compatible with the programming model + of the regular I2C controllers with a few exceptions. The I2C registers + start at an offset of 0xc00 (instead of 0), registers are 16 bytes + apart (rather than 4) and the controller does not support slave mode. - reg: Should contain I2C controller registers physical address and length. - interrupts: Should contain I2C controller interrupts. - address-cells: Address cells for I2C device address. @@ -53,10 +53,17 @@ Required properties: - fast-clk Tegra114: - div-clk + Tegra210: + - div-clk + - slow (only for nvidia,tegra210-i2c-vi compatible node) - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - i2c +- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must + include venc powergate node as vi i2c is part of VE power domain. + tegra210-i2c-vi: + - pd_venc - dmas: Must contain an entry for each entry in clock-names. See ../dma/dma.txt for details. - dma-names: Must include the following entries: From patchwork Wed Jun 10 06:02:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64397 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitlN-006p00-VX; Wed, 10 Jun 2020 05:59:03 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726262AbgFJGCt (ORCPT + 1 other); Wed, 10 Jun 2020 02:02:49 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11205 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726112AbgFJGCp (ORCPT ); Wed, 10 Jun 2020 02:02:45 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:13 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:45 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Jun 2020 23:02:45 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:45 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:44 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 02/18] arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C Date: Tue, 9 Jun 2020 23:02:24 -0700 Message-ID: <1591768960-31648-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768873; bh=aZpfEHCdQO79JYgaC0ZbsOUqg2JPUB+AZNA7nau630I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SfrZUwq0QbUFnEh+2mW1hBfrysLvlhF6RwRmdezH1QkEG85lHpyROhUwiWDqf8W+r GSHBw33OCuWGt072Nnz8stoyMkm4/UsdmTELHQWpHGKepSOWdrA64J9OoHAnCNwxQn D2oswMmu2yF76RaSkKE9KZpwyPQ2lPR53JpZFJ6gh3F16O8XebkaOJ7ys5q/6IIeTH Qouz8I7d5qgwqaoeae4xKtSAPCPJteqyP1M2NFXlK1x3rC/R2oMqGS1WgbQzI+xflS O5RXCIlXaBcckNbC1AfFoW4P8EKdB5rTIodjA2wCDTFiD8Un8yNoUdC0FYeyd1TJQN MT7oWQNjPtAlg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra210 VI I2C is in VE power domain and i2c-vi node should have power-domains property. Current Tegra210 i2c-vi device node is missing both VI I2C clocks and power-domains property. This patch adds them. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0865508..3a4ed10 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -376,6 +376,12 @@ compatible = "nvidia,tegra210-i2c-vi"; reg = <0x0 0x546c0000 0x0 0x00040000>; interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, + <&tegra_car TEGRA210_CLK_I2CSLOW>; + clock-names = "div-clk", "slow"; + resets = <&tegra_car TEGRA210_CLK_VI_I2C>; + reset-names = "i2c"; + power-domains = <&pd_venc>; status = "disabled"; }; }; From patchwork Wed Jun 10 06:02:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64413 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitn9-006p3l-4d; Wed, 10 Jun 2020 06:00:51 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726563AbgFJGEs (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:48 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6083 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726076AbgFJGCq (ORCPT ); Wed, 10 Jun 2020 02:02:46 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:45 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:45 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:45 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 03/18] i2c: tegra: Don't mark VI I2C as IRQ safe runtime PM Date: Tue, 9 Jun 2020 23:02:25 -0700 Message-ID: <1591768960-31648-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768920; bh=zxB65TqmmcKmPfWkLJU50AtZToCBrCGEYlb/JsyjY+U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DYbxS+vBHf/CFkVU1bqvqwYINCQE2Cho4VeoNEkp27HpOM79yynDNsQYKq8zKNxqN uNDDdTRfTIVchoCyH+Q/Oux/vy+Jd8snfgSva3gKEWF4YfyYb/ohGmle97s5WtpPmy QFu2V/mxulfh4MLcSDRj2OuKN4p9s6OimlRDYkizr5NncHUJhRxF+u5tl+flQcwo2a gK6mYo0JqzGbPWz9/fZ+sWdIuIBxLveZervEKrqsyB0b6JtbpTyYINFCaFBMgITOsz KS81raaW2rPuMFxFIW+qLN/jMsugbgmAn2E3UmGiNUaHydjhGjfFzEReFGuANPaZCU ucgFXExgFi8Sw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra VI I2C is part of VE power domain and typically used for camera usecases. VE power domain is not always on and is non-IRQ safe. So, IRQ safe device cannot be attached to a non-IRQ safe domain as it prevents powering off the PM domain and generic power domain driver will warn. Current driver marks all I2C devices as IRQ safe and VI I2C device does not require IRQ safe as it will not be used for atomic transfers. This patch has fix to make VI I2C as non-IRQ safe. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1577296..3be1018 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1750,7 +1750,15 @@ static int tegra_i2c_probe(struct platform_device *pdev) goto unprepare_slow_clk; } - pm_runtime_irq_safe(&pdev->dev); + /* + * VI I2C is in VE power domain which is not always on and not + * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ + * safe domain as it prevents powering off the PM domain. + * Also, VI I2C device don't need to use runtime IRQ safe as it will + * not be used for atomic transfers. + */ + if (!i2c_dev->is_vi) + pm_runtime_irq_safe(&pdev->dev); pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { ret = tegra_i2c_runtime_resume(&pdev->dev); From patchwork Wed Jun 10 06:02:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64410 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitn1-006p3l-9l; Wed, 10 Jun 2020 06:00:43 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726535AbgFJGEa (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:30 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11212 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbgFJGCr (ORCPT ); Wed, 10 Jun 2020 02:02:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:46 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:46 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:46 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:46 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 04/18] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume Date: Tue, 9 Jun 2020 23:02:26 -0700 Message-ID: <1591768960-31648-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768875; bh=FE3zccXsSJw4dQg1KvzPkaznm8tF4D5l77Bo/LLBkaM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qfnckt+MTSZJWTCS16Faw36qp6V4mxwiqEgki2rm3rbSG7DWgXxUyNTa3NxsA5cba nL44D04iaCA9aoZuHtZK411MM8affCmuMTh6zewkeNFu5BxqkFVSo25rLy1Tv6471g ZFIcKA/nexHymQuOA8t+0YnzzC7+l4mlSWlsdiXWWSBWMQa5AotXDOrcPrQik88It0 ktkE5PdpkesyxBBJ/Oits55fH7vcNBDOlF3BoMaL/aEK/OBt4YCzJKinScJilVkK0d 76Zc5Jp++lqeh52QQ1TYRzTJaTuZW7Ne35Rel815zpWVQ+/GozzX42sq5d1RCOACam xU+5Nv8brGFHA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no tegra_i2c_runtime_resume does not disable prior enabled clocks properly. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3be1018..dba38a5 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -668,7 +668,7 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) ret = clk_enable(i2c_dev->slow_clk); if (ret < 0) { dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; + goto disable_fast_clk; } } @@ -676,11 +676,18 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) if (ret < 0) { dev_err(i2c_dev->dev, "Enabling div clk failed, err %d\n", ret); - clk_disable(i2c_dev->fast_clk); - return ret; + goto disable_slow_clk; } return 0; + +disable_slow_clk: + if (i2c_dev->slow_clk) + clk_disable(i2c_dev->slow_clk); +disable_fast_clk: + if (!i2c_dev->hw->has_single_clk_source) + clk_disable(i2c_dev->fast_clk); + return ret; } static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) From patchwork Wed Jun 10 06:02:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64411 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitn2-006p3l-E6; Wed, 10 Jun 2020 06:00:45 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726527AbgFJGE2 (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:28 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10484 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726196AbgFJGCr (ORCPT ); Wed, 10 Jun 2020 02:02:47 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:47 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Jun 2020 23:02:47 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:46 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:46 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:46 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 05/18] i2c: tegra: Fix runtime resume to re-init VI I2C Date: Tue, 9 Jun 2020 23:02:27 -0700 Message-ID: <1591768960-31648-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768953; bh=h4CM4t4WxMI9i7DgepTWXatjnwpkOJJzA9gzSaOBero=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=KAjrC9lD0p/HvNV61ho+4D29CRe13r1QQelSD0lkdVUxrhyJwewXgsliDUjLa7aeq 9RGh+Fr4XSMtRjbW6Oi2Fy8XFBlIvs2jzKJPYQTkA6b0xtw46+tplCdtJW4vFkA54+ vCbPSoblOG3V2h4d2WaeiaGMg8WnF1PfCkZwHfAswCg3u2yy/ZqaYYUcE0u4vSG1z3 LJRgBE3zaXnLtxMsku4auiVJ5qya8P0zRYRS2yeHzP8M/98tU8/PF3ZBGDfPQ+clc1 aOYI79FoRW6xTSn+OfgjtZg3zyq9Sfh3jUXKu9baRRmtz8I9/F/LHyM5mG81yWA1dY LbCjKEXIwTCpA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus and is part of VE power domain. During suspend/resume VE power domain goes through power off/on. So, controller reset followed by i2c re-initialization is required after the domain power up. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index dba38a5..650240d 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -293,6 +293,8 @@ struct tegra_i2c_dev { bool is_curr_atomic_xfer; }; +static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit); + static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) { @@ -679,8 +681,22 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) goto disable_slow_clk; } + /* + * VI I2C device is attached to VE power domain which goes through + * power ON/OFF during PM runtime resume/suspend. So, controller + * should go through reset and need to re-initialize after power + * domain ON. + */ + if (i2c_dev->is_vi) { + ret = tegra_i2c_init(i2c_dev, true); + if (ret) + goto disable_div_clk; + } + return 0; +disable_div_clk: + clk_disable(i2c_dev->div_clk); disable_slow_clk: if (i2c_dev->slow_clk) clk_disable(i2c_dev->slow_clk); From patchwork Wed Jun 10 06:02:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64412 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitn5-006p3l-6N; Wed, 10 Jun 2020 06:00:47 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726365AbgFJGE1 (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:27 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10491 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726249AbgFJGCr (ORCPT ); Wed, 10 Jun 2020 02:02:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:47 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:47 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:47 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:47 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:47 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 06/18] i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c Date: Tue, 9 Jun 2020 23:02:28 -0700 Message-ID: <1591768960-31648-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768954; bh=1s9dzZ23FpCC5jCiBWHmtIJv2ULCqfj+qrwdZQCyNRQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=r7oRzXIKUhxMcBNbgq4vp24n2h4QUBgwSI9hQ/kngELAnqeJ8ckqvEXVtN+BWtqIP B03QHpanxhz4LLCNYm54JqW80aURdIKXuk9I4/XAJA5t0n9pO/2sX3aHXcCNA8o6tj ceyKx66F6eUvcdYRj7cSYGYgqfmQ29Rpnh/gx1ZKSp2/eAJf9+mDAymF+THtOHGJNd dw5iTJKr+oQMFSJoF3wDKXoiz8tASlJrNjYbJPBtNBjh/pJ5mAycIFuMTZbo2toi6a QK67iS03NNcw7e6Ez/pCdEsWJeqDB0sbAZlfy0NicDVfo2HdCqsLApI22OQQ1TM7D4 ZroIZ3lhhomGw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no VI I2C is on host1x bus so APB DMA can't be used for Tegra210 VI I2C and there are no tx and rx dma channels for VI I2C. So, avoid attempt of requesting DMA channels. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 650240d..ed99dfe 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -421,7 +421,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) dma_addr_t dma_phys; int err; - if (!i2c_dev->hw->has_apb_dma) + if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) return 0; if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { From patchwork Wed Jun 10 06:02:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64398 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitli-006p0Q-9t; Wed, 10 Jun 2020 05:59:22 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726316AbgFJGDA (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:00 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6094 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726251AbgFJGCt (ORCPT ); Wed, 10 Jun 2020 02:02:49 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:48 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:47 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 07/18] media: tegra-video: Fix channel format alignment Date: Tue, 9 Jun 2020 23:02:29 -0700 Message-ID: <1591768960-31648-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768923; bh=8GJbUvoTqNXQhoilqMQO06MgCPv5IgO6eahUeR7/0ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=pbejqEq1pq31KzLzJ/BnpGUQSpGRX3kiKwRtDSyFNjxMx2bWJZCoRynik19X8Eo+N SE0fFIHiGkxfgcnfbJ8s42EkUjVAlHInPXIx6Hv1Ean21ghAEoDwsMJsTXitbeuPoq 8RoHlGMhjAveHXUQ+ic3800PIaBZV1mSGlCw9z+Nl1iJxlwrzcIucGwJQCaHHqDfxK alwAekJbgXRDMvuAYRZMR7WGhRmIFb02b3qKt0fQd+qPCVhnCoS3cZ5YdVh3JN4x8a 9J4b4oVZB0su9+0acnNE8hr2UFTmoB8AbTjZP200O+09uWESf2tEvZQZgW78UXllO8 c5MUQF7Rz6+jw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 1b5e660..d621ebc 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per From patchwork Wed Jun 10 06:02:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64400 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitln-006p0Q-MJ; Wed, 10 Jun 2020 05:59:28 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726300AbgFJGC7 (ORCPT + 1 other); Wed, 10 Jun 2020 02:02:59 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11223 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726261AbgFJGCt (ORCPT ); Wed, 10 Jun 2020 02:02:49 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:48 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:48 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:48 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 08/18] media: tegra-video: Enable TPG based on kernel config Date: Tue, 9 Jun 2020 23:02:30 -0700 Message-ID: <1591768960-31648-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768877; bh=ds7oxXGxAuyDw53E4hJLEBinWlNAsgh9dJ6sWX9tefI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BQwzfSLdjUIEyaGbiz3poyADg1J8F4kojYa1qL/xE03oyGbWI0SttUQP4HsX9t6oX 9ofh8sMDvMr0Fw9qPo9SpmlgfzA2eLSeexSbRO1oXeU4o+ClO/OM0MA2FYqhxA19mq /5Nuikm+kRkny95KrYL9B4uk8d1XwqRxgWFacBtqLt1Uq0iHuLAFl4lWmqA7nPUMX+ X8oOT0sTDBabFE88yJGpuhqZpXVxjc2UZlb2fZICIdUfSLMbmfKtGnyXVEjYlvOEKr i47k2uXRTqmfOxBlA1jFQB8pnf491x0K+ysH26yk1/iYhGDfa/HzfsfLiR1Qva5bwd Pe8TdIpiipHig== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra internal TPG mode is only for Tegra vi and csi testing without a real sensor and driver should default support real sensor. So, This patch adds CONFIG_VIDEO_TEGRA_TPG and enables Tegra internal TPG mode only when this config is selected. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 6 +++++ drivers/staging/media/tegra-video/csi.c | 38 +++++++++++++++++++++++----- drivers/staging/media/tegra-video/tegra210.c | 6 +++++ drivers/staging/media/tegra-video/vi.c | 13 +++++++--- drivers/staging/media/tegra-video/video.c | 23 +++++++++-------- 5 files changed, 65 insertions(+), 21 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index f6c61ec..566da62 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -10,3 +10,9 @@ config VIDEO_TEGRA To compile this driver as a module, choose M here: the module will be called tegra-video. + +config VIDEO_TEGRA_TPG + bool "NVIDIA Tegra VI driver TPG mode" + depends on VIDEO_TEGRA + help + Say yes here to enable Tegra internal TPG mode diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 40ea195..fb667df 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -62,6 +62,9 @@ static int csi_enum_bus_code(struct v4l2_subdev *subdev, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_mbus_code_enum *code) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) return -EINVAL; @@ -76,6 +79,9 @@ static int csi_get_format(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + fmt->format = csi_chan->format; return 0; @@ -121,6 +127,9 @@ static int csi_enum_framesizes(struct v4l2_subdev *subdev, { unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) return -EINVAL; @@ -148,6 +157,9 @@ static int csi_enum_frameintervals(struct v4l2_subdev *subdev, const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; int index; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + /* one framerate per format and resolution */ if (fie->index > 0) return -EINVAL; @@ -172,6 +184,9 @@ static int csi_set_format(struct v4l2_subdev *subdev, const struct v4l2_frmsize_discrete *sizes; unsigned int i; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, ARRAY_SIZE(tegra_csi_tpg_sizes), width, height, @@ -208,6 +223,9 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOIOCTLCMD; + vfi->interval.numerator = 1; vfi->interval.denominator = csi_chan->framerate; @@ -311,8 +329,12 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) subdev = &chan->subdev; v4l2_subdev_init(subdev, &tegra_csi_ops); subdev->dev = csi->dev; - snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", - chan->csi_port_num); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", + chan->csi_port_num); + else + snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", + kbasename(chan->of_node->full_name)); v4l2_set_subdevdata(subdev, chan); subdev->fwnode = of_fwnode_handle(chan->of_node); @@ -405,11 +427,13 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_csi_tpg_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto cleanup; + } } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3baa4e3..3492a8a 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -631,7 +631,11 @@ const struct tegra_vi_soc tegra210_vi_soc = { .ops = &tegra210_vi_ops, .hw_revision = 3, .vi_max_channels = 6, +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) .vi_max_clk_hz = 499200000, +#else + .vi_max_clk_hz = 998400000, +#endif }; /* Tegra210 CSI PHY registers accessors */ @@ -957,7 +961,9 @@ static const char * const tegra210_csi_cil_clks[] = { "cilab", "cilcd", "cile", +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) "csi_tpg", +#endif }; /* Tegra210 CSI operations */ diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index d621ebc..0197f4e 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -565,6 +565,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) { int ret; +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) /* add test pattern control handler to v4l2 device */ v4l2_ctrl_new_std_menu_items(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_TEST_PATTERN, @@ -576,6 +577,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#endif /* setup the controls */ ret = v4l2_ctrl_handler_setup(&chan->ctrl_handler); @@ -918,10 +920,13 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, "failed to allocate tpg channels: %d\n", ret); - goto free_chans; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_tpg_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate tpg channels: %d\n", ret); + goto free_chans; + } } ret = tegra_vi_channels_init(vi); diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/media/tegra-video/video.c index 30816aa..e50bd70 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -60,15 +60,17 @@ static int host1x_video_probe(struct host1x_device *dev) if (ret < 0) goto unregister_v4l2; - /* - * Both vi and csi channels are available now. - * Register v4l2 nodes and create media links for TPG. - */ - ret = tegra_v4l2_nodes_setup_tpg(vid); - if (ret < 0) { - dev_err(&dev->dev, - "failed to setup tpg graph: %d\n", ret); - goto device_exit; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + /* + * Both vi and csi channels are available now. + * Register v4l2 nodes and create media links for TPG. + */ + ret = tegra_v4l2_nodes_setup_tpg(vid); + if (ret < 0) { + dev_err(&dev->dev, + "failed to setup tpg graph: %d\n", ret); + goto device_exit; + } } return 0; @@ -91,7 +93,8 @@ static int host1x_video_remove(struct host1x_device *dev) { struct tegra_video_device *vid = dev_get_drvdata(&dev->dev); - tegra_v4l2_nodes_cleanup_tpg(vid); + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_v4l2_nodes_cleanup_tpg(vid); host1x_device_exit(dev); From patchwork Wed Jun 10 06:02:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64401 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitlq-006p0Q-UA; Wed, 10 Jun 2020 05:59:31 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726291AbgFJGC6 (ORCPT + 1 other); Wed, 10 Jun 2020 02:02:58 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10502 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726264AbgFJGCu (ORCPT ); Wed, 10 Jun 2020 02:02:50 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:49 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:49 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:49 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:48 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 09/18] media: tegra-video: Update format lookup to offset based Date: Tue, 9 Jun 2020 23:02:31 -0700 Message-ID: <1591768960-31648-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768956; bh=5U56MbpoGgbizDY87xBQZF5BWeIIcAyUuev+l62V8Co=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=RNjlzi76Vn2q4JBEfvLU2osE/DD4dy8kMevQ9VmOOUByhQb4Z3inJI2VcMctdQF1I cI4WsINjdLOFjCsf7oPILdi52bjPkGtPpp07PQSlO0Q0wzzrNS5zMMWioBg3GraWs7 9e8EmABejoCWgLXwVVWPT9XHdnf8+cG9YNz4PMke7iBJYBQw6655fUcjMWOndthYhw BTRP7V5mP4JpYkHhK3CNxV8G6DGToDA7VCwF8VKWnAgsWbbMtHCeXmYKL9OEYw8ry7 gT8xcyNpJ0tVLGsYJiEe0ckE2jdpZeHLcswRU0N9etfrUa0D7AU+gkqspRrQrDQ+Ej yTt1d+IigWoiw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Tegra VI supported video formats are more for non TPG and there can be multiple pixel formats for the same media bus format. This patch updates the helper function for format lookup based on mbus code from pre-defined Tegra supported format list to look from the specified list index offset. Offset based look up is used with sensor device graph (non TPG) where format enumeration can list all supported formats for the specific sensor mbus codes. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 0197f4e..52d751f 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -53,11 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) } static int tegra_get_format_idx_by_code(struct tegra_vi *vi, - unsigned int code) + unsigned int code, + unsigned int offset) { unsigned int i; - for (i = 0; i < vi->soc->nformats; ++i) { + for (i = offset; i < vi->soc->nformats; ++i) { if (vi->soc->video_formats[i].code == code) return i; } @@ -598,11 +599,12 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_zero(chan->tpg_fmts_bitmap, MAX_FORMAT_NUM); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_SRGGB10_1X10); + MEDIA_BUS_FMT_SRGGB10_1X10, 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_RGB888_1X32_PADHI); + MEDIA_BUS_FMT_RGB888_1X32_PADHI, + 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); } From patchwork Wed Jun 10 06:02:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64399 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitlj-006p0Q-Ib; Wed, 10 Jun 2020 05:59:24 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726310AbgFJGC7 (ORCPT + 1 other); Wed, 10 Jun 2020 02:02:59 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11231 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726268AbgFJGCu (ORCPT ); Wed, 10 Jun 2020 02:02:50 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:50 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:50 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:49 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:49 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:49 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 10/18] dt-bindings: tegra: Document VI and CSI port nodes Date: Tue, 9 Jun 2020 23:02:32 -0700 Message-ID: <1591768960-31648-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768878; bh=wPUjcK5pjatayPbHQg+cG5OdMe7PMrZuDRJsqwl5MoU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ei59UQXi7yEOg3WW32Mp1G+liqrIbq6KgKYXkk5nfw4KS4XF6G1yTXTM4NS+8WpFB 74gYnQSUQz5zn6ViJqqtSIM4vz2NRmAYhgfO+U1QT4Uk2IcGrVB8/ajaCkbm8C3iVj bUWH2UR0uUDnV3vvyjurqDumaWcl6tCQ5uAxKeH4EvESVuDWISRSDc3Ysn8xgh+ha4 nVGS/9bnwsxhQ3HLVmgoGyjACSF6pWPzN7tnqR23rr3pAzKVpxylFeR78yZnHwFq4w OhV1OyaWPXqNHwyFlikaNPLlwrGQNcAUgbP0Y5uRp1HVP4HK5iw9RcpgksXCpW//UT AJJlQOjq0R06g== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch documents Tegra VI and CSI port and endpoint nodes along with the other required properties. Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 4731921..f70a838 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -65,6 +65,48 @@ of the following host1x client modules: - power-domains: Must include sor powergate node as csicil is in SOR partition. + Optional properties for csi node: + + - channel nodes: Max upto 6 channels/streams are supported with each CSI + brick can as either x4 or x2 based on hw connectivity to sensor. + + Required properties: + - reg: channel/stream index + - nvidia,mipi-calibrate: Should contain a phandle and a specifier + specifying which pads are used by this CSI port and need to be + calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. + + - port: CSI port node and its endpoint nodes as per device graph + bindings defined in Documentation/devicetree/bindings/graph.txt. + Required properties: + - reg: csi port index based on hw csi lanes connectivity to the + sensor. + - bus-width: number of lanes used by this port. Supported lanes + are 1/2/4. + - endpoint@0: sink node + Required properties: + - reg: endpoint id. This is used to retrieve pad for creating + media link + - remote-endpoint: phandle to sensor endpoint + - endpoint@1: source node + - reg: endpoint id. This is used to retrieve pad for creating + media link + - remote-endpoint: phandle to vi port endpoint + + Optional properties for vi node: + - ports: Video port nodes and endpoint nodes as per device graph bindings + defined in Documentation/devicetree/bindings/graph.txt + Max 6 ports are supported and each port should have one endpoint node. + + Required properties: + - port: VI port node and its sink endpoint node + Required properties: + - reg: should match port index + - endpoint@0: sink node + Required properties: + - reg: endpoint id must be 0 + - remote-endpoint: phandle to CSI endpoint node. + - epp: encoder pre-processor Required properties: @@ -340,6 +382,22 @@ Example: ranges = <0x0 0x0 0x54080000 0x2000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + imx219_vi_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&imx219_csi_out0>; + }; + }; + }; + csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; @@ -362,6 +420,35 @@ Example: <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + nvidia,mipi-calibrate = <&mipi 0x001>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bus-width = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + imx219_csi_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&imx219_out0>; + }; + + imx219_csi_out0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_vi_in0>; + }; + }; + }; }; }; From patchwork Wed Jun 10 06:02:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64406 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmd-006p2i-4G; Wed, 10 Jun 2020 06:00:21 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726496AbgFJGEA (ORCPT + 1 other); Wed, 10 Jun 2020 02:04:00 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10508 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbgFJGCv (ORCPT ); Wed, 10 Jun 2020 02:02:51 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:37 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:50 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Jun 2020 23:02:50 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:50 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:50 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:50 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 11/18] media: tegra-video: Add support for external sensor capture Date: Tue, 9 Jun 2020 23:02:33 -0700 Message-ID: <1591768960-31648-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768957; bh=+6MlE4NZLWb4eURi+NDfXF5tuEnXU1Oud5JtJo5ze7k=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=LbtFr6SCp/S0JHMuFc6wLBwBibtIKTKeamjob576iSX9Js/B1PCQSTx1uJfNia8/Y /zN0jVjfDCi1GeWHbn26i3McOc9QY9G1ZleAnc9ZjWMq7k0XTaDMTkwxxmbwV4xpsG mpbab09KTOhFHHAUCanbYpT7hFRMOVsU+1eDuktyVhYkn6C+ifuR6+Pag5tHyEFMOg XwZ6jX1+2TBRxUdSpz9EfDz+C/Xv6xZPvrBEkbMGVvJny+2iZZ60cl8TTSJz078BSc laxObUPXnKW8brpCk33mkTZNaX9ospwqRuxrHAEsDPgQcYr7HS+U/L1SPhxWsNpdgO 7tmC49m+7FBpg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds support to capture from the external sensor based on device graph in the device tree. Driver walks through the device graph to create media links between the entities and registers and unregisters video devices when the corresponding sub-devices are bound and unbound. Channel formats are enumerated based on available formats from the sensor and the corresponding matched formats from the Tegra supported video formats list. Each Tegra CSI instance can be configured as 4-lane or 2-lane based on supported lane configuration from the sensor through the device tree. Currently this driver supports V4L2 video node centric only. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 1 + drivers/staging/media/tegra-video/csi.c | 128 +++++- drivers/staging/media/tegra-video/csi.h | 2 + drivers/staging/media/tegra-video/tegra210.c | 2 +- drivers/staging/media/tegra-video/vi.c | 623 +++++++++++++++++++++++++-- drivers/staging/media/tegra-video/vi.h | 23 +- 6 files changed, 727 insertions(+), 52 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index 566da62..1f35da4 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -5,6 +5,7 @@ config VIDEO_TEGRA depends on VIDEO_V4L2 select MEDIA_CONTROLLER select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE help Choose this option if you have an NVIDIA Tegra SoC. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index fb667df..14e9050 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -285,26 +285,102 @@ static const struct v4l2_subdev_ops tegra_csi_ops = { .pad = &tegra_csi_pad_ops, }; +static int tegra_csi_channel_alloc(struct tegra_csi *csi, + struct device_node *node, + unsigned int port_num, unsigned int lanes, + unsigned int num_pads) +{ + struct tegra_csi_channel *chan; + + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + list_add_tail(&chan->list, &csi->csi_chans); + chan->csi = csi; + chan->csi_port_num = port_num; + chan->numlanes = lanes; + chan->of_node = node; + chan->numpads = num_pads; + if (num_pads & 0x2) { + chan->pads[0].flags = MEDIA_PAD_FL_SINK; + chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; + } else { + chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + } + + return 0; +} + static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) { struct device_node *node = csi->dev->of_node; unsigned int port_num; - struct tegra_csi_channel *chan; unsigned int tpg_channels = csi->soc->csi_max_channels; + int ret; /* allocate CSI channel for each CSI x2 ports */ for (port_num = 0; port_num < tpg_channels; port_num++) { - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; - - list_add_tail(&chan->list, &csi->csi_chans); - chan->csi = csi; - chan->csi_port_num = port_num; - chan->numlanes = 2; - chan->of_node = node; - chan->numpads = 1; - chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_csi_channels_alloc(struct tegra_csi *csi) +{ + struct device_node *node = csi->dev->of_node; + struct device_node *channel; + struct device_node *port; + struct device_node *ep; + unsigned int lanes, port_num, num_pads; + int ret; + + for_each_child_of_node(node, channel) { + if (!of_node_name_eq(channel, "channel")) + continue; + + num_pads = 0; + port = of_get_child_by_name(channel, "port"); + if (!port) + continue; + + ret = of_property_read_u32(port, "reg", &port_num); + if (ret < 0) + continue; + + if (port_num >= csi->soc->csi_max_channels) { + dev_err(csi->dev, "invalid port num %d\n", port_num); + return -EINVAL; + } + + ret = of_property_read_u32(port, "bus-width", &lanes); + if (ret < 0) { + dev_err(csi->dev, "missing CSI bus-width\n"); + return -EINVAL; + } + + if (!lanes || ((lanes & (lanes - 1)) != 0) || + lanes > CSI_MAX_LANES_PER_BRICK) { + dev_err(csi->dev, "invalid CSI bus-width\n"); + return -EINVAL; + } + + for_each_child_of_node(port, ep) { + if (!of_node_name_eq(ep, "endpoint")) + continue; + + num_pads++; + } + + if (num_pads == TEGRA_CSI_PADS_NUM) { + ret = tegra_csi_channel_alloc(csi, channel, port_num, + lanes, num_pads); + if (ret < 0) + return ret; + } } return 0; @@ -350,6 +426,15 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) return ret; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = v4l2_async_register_subdev(subdev); + if (ret < 0) { + dev_err(csi->dev, + "failed to register subdev: %d\n", ret); + return ret; + } + } + return 0; } @@ -389,8 +474,12 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { subdev = &chan->subdev; - if (subdev->dev) + if (subdev->dev) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_unregister_subdev(subdev); media_entity_cleanup(&subdev->entity); + } + list_del(&chan->list); kfree(chan); } @@ -427,13 +516,14 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; - } + else + ret = tegra_csi_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate channels: %d\n", ret); + goto cleanup; } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 93bd2a0..b7b754a 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -7,6 +7,7 @@ #define __TEGRA_CSI_H__ #include +#include #include /* @@ -16,6 +17,7 @@ * CILB. */ #define CSI_PORTS_PER_BRICK 2 +#define CSI_MAX_LANES_PER_BRICK 4 /* each CSI channel can have one sink and one source pads */ #define TEGRA_CSI_PADS_NUM 2 diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3492a8a..4f5080a 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -230,7 +230,7 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) tegra_channel_capture_setup(chan); /* recover CSI block */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, false); tegra_csi_error_recover(subdev); } diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 52d751f..6f320c1 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) return container_of(vb, struct tegra_channel_buffer, buf); } +static inline struct tegra_vi_graph_entity * +to_tegra_vi_graph_entity(struct v4l2_async_subdev *asd) +{ + return container_of(asd, struct tegra_vi_graph_entity, asd); +} + static int tegra_get_format_idx_by_code(struct tegra_vi *vi, unsigned int code, unsigned int offset) @@ -146,7 +153,7 @@ static void tegra_channel_buffer_queue(struct vb2_buffer *vb) } struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) +tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor) { struct media_pad *pad; struct v4l2_subdev *subdev; @@ -156,6 +163,24 @@ tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) entity = pad->entity; subdev = media_entity_to_v4l2_subdev(entity); + if (sensor) { + while (1) { + if ((pad->index - 1) < 0) + break; + + pad = &entity->pads[pad->index - 1]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_entity_remote_pad(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + } + } + return subdev; } @@ -165,7 +190,15 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) int ret; /* stream CSI */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, !on); + ret = v4l2_subdev_call(subdev, video, s_stream, on); + if (on && ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + subdev = tegra_channel_get_remote_subdev(chan, on); ret = v4l2_subdev_call(subdev, video, s_stream, on); if (on && ret < 0 && ret != -ENOIOCTLCMD) return ret; @@ -252,7 +285,7 @@ static int tegra_channel_g_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); return v4l2_g_parm_cap(&chan->video, subdev, a); } @@ -262,7 +295,7 @@ static int tegra_channel_s_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); return v4l2_s_parm_cap(&chan->video, subdev, a); } @@ -284,7 +317,7 @@ static int tegra_channel_enum_framesizes(struct file *file, void *fh, fse.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); ret = v4l2_subdev_call(subdev, pad, enum_frame_size, NULL, &fse); if (ret) return ret; @@ -316,7 +349,7 @@ static int tegra_channel_enum_frameintervals(struct file *file, void *fh, fie.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); ret = v4l2_subdev_call(subdev, pad, enum_frame_interval, NULL, &fie); if (ret) return ret; @@ -335,6 +368,9 @@ static int tegra_channel_enum_format(struct file *file, void *fh, unsigned int index = 0, i; unsigned long *fmts_bitmap = chan->tpg_fmts_bitmap; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + fmts_bitmap = chan->fmts_bitmap; + if (f->index >= bitmap_weight(fmts_bitmap, MAX_FORMAT_NUM)) return -EINVAL; @@ -391,8 +427,9 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + int ret; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); pad_cfg = v4l2_subdev_alloc_pad_config(subdev); if (!pad_cfg) return -ENOMEM; @@ -412,7 +449,10 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -452,8 +492,11 @@ static int tegra_channel_set_format(struct file *file, void *fh, fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - subdev = tegra_channel_get_remote_subdev(chan); - v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -463,15 +506,52 @@ static int tegra_channel_set_format(struct file *file, void *fh, return 0; } +static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) +{ + int ret, index; + const struct tegra_video_format *fmtinfo; + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + /* + * Initialize channel format to the sub-device active format if there + * is corresponding match in the Tegra supported video formats. + */ + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret) + return ret; + + index = tegra_get_format_idx_by_code(chan->vi, fmt.format.code, 0); + fmtinfo = &chan->vi->soc->video_formats[index]; + if (!fmtinfo) + return -EINVAL; + + chan->fmtinfo = fmtinfo; + v4l2_fill_pix_format(&chan->format, &fmt.format); + chan->format.pixelformat = chan->fmtinfo->fourcc; + chan->format.bytesperline = chan->format.width * chan->fmtinfo->bpp; + chan->format.sizeimage = chan->format.bytesperline * + chan->format.height; + tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + + return 0; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { - /* currently driver supports internal TPG only */ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + if (inp->index) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; - strscpy(inp->name, "Tegra TPG", sizeof(inp->name)); + subdev = tegra_channel_get_remote_subdev(chan, true); + strscpy(inp->name, subdev->name, sizeof(inp->name)); return 0; } @@ -578,6 +658,19 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#else + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_ctrl_add_handler(&chan->ctrl_handler, subdev->ctrl_handler, + NULL, true); + if (ret < 0) { + dev_err(chan->vi->dev, + "failed to add subdev %s ctrl handler: %d\n", + subdev->name, ret); + v4l2_ctrl_handler_free(&chan->ctrl_handler); + return ret; + } #endif /* setup the controls */ @@ -608,6 +701,57 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_set(chan->tpg_fmts_bitmap, index, 1); } +static void vi_fmts_bitmap_init(struct tegra_vi_channel *chan) +{ + int index, ret, match_code = 0; + struct v4l2_subdev *subdev; + struct v4l2_subdev_mbus_code_enum code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM); + + /* + * Set the bitmap bits based on all the matched formats between the + * available media bus formats of sub-device and the pre-defined Tegra + * supported video formats. + */ + subdev = tegra_channel_get_remote_subdev(chan, true); + while (1) { + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code, + NULL, &code); + if (ret < 0) + break; + + index = tegra_get_format_idx_by_code(chan->vi, code.code, 0); + while (index >= 0) { + bitmap_set(chan->fmts_bitmap, index, 1); + if (!match_code) + match_code = code.code; + /* look for other formats with same mbus code */ + index = tegra_get_format_idx_by_code(chan->vi, + code.code, + index + 1); + } + + code.index++; + } + + /* + * Set the bitmap bit corresponding to default tegra video format if + * there are no matched formats. + */ + if (!match_code) { + match_code = tegra_default_format.code; + index = tegra_get_format_idx_by_code(chan->vi, match_code, 0); + if (index >= 0) + bitmap_set(chan->fmts_bitmap, index, 1); + } + + /* initialize channel format to the sub-device active format */ + tegra_channel_set_subdev_active_fmt(chan); +} + static void tegra_channel_cleanup(struct tegra_vi_channel *chan) { v4l2_ctrl_handler_free(&chan->ctrl_handler); @@ -720,6 +864,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) goto free_v4l2_ctrl_hdl; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_notifier_init(&chan->notifier); + return 0; free_v4l2_ctrl_hdl: @@ -733,29 +880,85 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) return ret; } -static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, + struct device_node *node) { struct tegra_vi_channel *chan; + + /* + * Do not use devm_kzalloc as memory is freed immediately + * when device instance is unbound but application might still + * be holding the device node open. Channel memory allocated + * with kzalloc is freed during video device release callback. + */ + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->vi = vi; + chan->portno = port_num; + chan->of_node = node; + list_add_tail(&chan->list, &vi->vi_chans); + + return 0; +} + +static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +{ unsigned int port_num; unsigned int nchannels = vi->soc->vi_max_channels; + int ret; for (port_num = 0; port_num < nchannels; port_num++) { - /* - * Do not use devm_kzalloc as memory is freed immediately - * when device instance is unbound but application might still - * be holding the device node open. Channel memory allocated - * with kzalloc is freed during video device release callback. - */ - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; + ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_vi_channels_alloc(struct tegra_vi *vi) +{ + struct device_node *node = vi->dev->of_node; + struct device_node *ep = NULL; + struct device_node *ports; + struct device_node *port; + unsigned int port_num; + int ret; + + ports = of_get_child_by_name(node, "ports"); + if (!ports) + return -ENODEV; + + for_each_child_of_node(ports, port) { + if (!of_node_name_eq(port, "port")) + continue; + + ret = of_property_read_u32(port, "reg", &port_num); + if (ret < 0) + continue; + + if (port_num > vi->soc->vi_max_channels) { + ret = -EINVAL; + dev_err(vi->dev, "invalid port num %d\n", port_num); + goto cleanup; + } - chan->vi = vi; - chan->portno = port_num; - list_add_tail(&chan->list, &vi->vi_chans); + ep = of_get_next_child(port, NULL); + if (ep && of_node_name_eq(ep, "endpoint")) { + of_node_put(ep); + ret = tegra_vi_channel_alloc(vi, port_num, port); + if (ret < 0) + goto cleanup; + } } return 0; + +cleanup: + of_node_put(ports); + return ret; } static int tegra_vi_channels_init(struct tegra_vi *vi) @@ -909,6 +1112,352 @@ static int __maybe_unused vi_runtime_suspend(struct device *dev) return 0; } +/* + * Graph Management + */ +static struct tegra_vi_graph_entity * +tegra_vi_graph_find_entity(struct tegra_vi_channel *chan, + const struct fwnode_handle *fwnode) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + if (entity->asd.match.fwnode == fwnode) + return entity; + } + + return NULL; +} + +static int tegra_vi_graph_build(struct tegra_vi_channel *chan, + struct tegra_vi_graph_entity *entity) +{ + struct tegra_vi *vi = chan->vi; + struct tegra_vi_graph_entity *ent; + struct fwnode_handle *ep = NULL; + struct v4l2_fwnode_link link; + struct media_entity *local = entity->entity; + struct media_entity *remote; + struct media_pad *local_pad; + struct media_pad *remote_pad; + u32 link_flags = MEDIA_LNK_FL_ENABLED; + int ret = 0; + + dev_dbg(vi->dev, "creating links for entity %s\n", local->name); + + while (1) { + ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode, + ep); + if (!ep) + break; + + ret = v4l2_fwnode_parse_link(ep, &link); + if (ret < 0) { + dev_err(vi->dev, "failed to parse link for %pOF: %d\n", + to_of_node(ep), ret); + continue; + } + + if (link.local_id >= local->num_pads) { + dev_err(vi->dev, "invalid endpoint id %u for %pOF\n", + link.local_id, to_of_node(link.local_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + local_pad = &local->pads[link.local_id]; + /* + * Remote node is vi node. So use channel video entity and pad + * as remote/sink. + */ + if (link.remote_node == of_fwnode_handle(vi->dev->of_node)) { + remote = &chan->video.entity; + remote_pad = &chan->pad; + goto create_link; + } + + /* + * Skip sink ports, they will be processed from the other end + * of the link. + */ + if (local_pad->flags & MEDIA_PAD_FL_SINK) { + dev_dbg(vi->dev, "skipping sink port %pOF:%u\n", + to_of_node(link.local_node), link.local_id); + v4l2_fwnode_put_link(&link); + continue; + } + + /* find the remote entity from notifier list */ + ent = tegra_vi_graph_find_entity(chan, link.remote_node); + if (!ent) { + dev_err(vi->dev, "no entity found for %pOF\n", + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -ENODEV; + break; + } + + remote = ent->entity; + if (link.remote_id >= remote->num_pads) { + dev_err(vi->dev, "invalid endpoint id %u for %pOF\n", + link.remote_id, to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + remote_pad = &remote->pads[link.remote_id]; + +create_link: + dev_dbg(vi->dev, "creating %s:%u -> %s:%u link\n", + local->name, local_pad->index, + remote->name, remote_pad->index); + + ret = media_create_pad_link(local, local_pad->index, + remote, remote_pad->index, + link_flags); + v4l2_fwnode_put_link(&link); + if (ret < 0) { + dev_err(vi->dev, + "failed to create %s:%u -> %s:%u link: %d\n", + local->name, local_pad->index, + remote->name, remote_pad->index, ret); + break; + } + } + + fwnode_handle_put(ep); + return ret; +} + +static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + struct v4l2_subdev *subdev; + struct tegra_vi_channel *chan; + struct tegra_vi *vi; + int ret; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + dev_dbg(vi->dev, "notify complete, all subdevs registered\n"); + + ret = video_register_device(&chan->video, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + dev_err(vi->dev, + "failed to register video device: %d\n", ret); + goto unregister_video; + } + + /* create links between the entities */ + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + ret = tegra_vi_graph_build(chan, entity); + if (ret < 0) + goto unregister_video; + } + + ret = tegra_channel_setup_ctrl_handler(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to setup channel controls: %d\n", ret); + goto unregister_video; + } + + vi_fmts_bitmap_init(chan); + subdev = tegra_channel_get_remote_subdev(chan, false); + v4l2_set_subdev_hostdata(subdev, chan); + + return 0; + +unregister_video: + video_unregister_device(&chan->video); + return ret; +} + +static int tegra_vi_graph_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + /* + * Locate the entity corresponding to the bound subdev and store the + * subdev pointer. + */ + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (!entity) { + dev_err(vi->dev, "no entity for subdev %s\n", subdev->name); + return -EINVAL; + } + + if (entity->subdev) { + dev_err(vi->dev, "duplicate subdev for node %pOF\n", + to_of_node(entity->asd.match.fwnode)); + return -EINVAL; + } + + dev_dbg(vi->dev, "subdev %s bound\n", subdev->name); + entity->entity = &subdev->entity; + entity->subdev = subdev; + + return 0; +} + +static void tegra_vi_graph_notify_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + video_unregister_device(&chan->video); + + media_entity_remove_links(&chan->video.entity); + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (entity) { + if (entity->entity) + media_entity_remove_links(entity->entity); + entity->entity = NULL; + entity->subdev = NULL; + } + + dev_dbg(vi->dev, "subdev %s unbind\n", subdev->name); +} + +static const struct v4l2_async_notifier_operations tegra_vi_async_ops = { + .bound = tegra_vi_graph_notify_bound, + .complete = tegra_vi_graph_notify_complete, + .unbind = tegra_vi_graph_notify_unbind, +}; + +static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, + struct fwnode_handle *fwnode) +{ + struct tegra_vi *vi = chan->vi; + struct fwnode_handle *ep = NULL; + struct fwnode_handle *remote = NULL; + struct v4l2_async_subdev *asd; + struct device_node *node = NULL; + int ret; + + dev_dbg(vi->dev, "parsing node %pOF\n", to_of_node(fwnode)); + + /* parse all the remote entities and put them into the list */ + for_each_endpoint_of_node(to_of_node(fwnode), node) { + ep = of_fwnode_handle(node); + remote = fwnode_graph_get_remote_port_parent(ep); + if (!remote) { + dev_err(vi->dev, + "remote device at %pOF not found\n", node); + ret = -EINVAL; + goto cleanup; + } + + /* skip entities that are already processed */ + if (remote == dev_fwnode(vi->dev) || + tegra_vi_graph_find_entity(chan, remote)) { + fwnode_handle_put(remote); + continue; + } + + asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, + remote, sizeof(struct tegra_vi_graph_entity)); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + dev_err(vi->dev, + "failed to add subdev to notifier: %d\n", ret); + fwnode_handle_put(remote); + goto cleanup; + } + + ret = tegra_vi_graph_parse_one(chan, remote); + if (ret < 0) { + fwnode_handle_put(remote); + goto cleanup; + } + + fwnode_handle_put(remote); + } + + return 0; + +cleanup: + dev_err(vi->dev, "failed parsing the graph: %d\n", ret); + v4l2_async_notifier_cleanup(&chan->notifier); + of_node_put(node); + return ret; +} + +static int tegra_vi_graph_init(struct tegra_vi *vi) +{ + struct tegra_video_device *vid = dev_get_drvdata(vi->client.host); + struct tegra_vi_channel *chan; + struct fwnode_handle *fwnode = dev_fwnode(vi->dev); + int ret; + struct fwnode_handle *remote = NULL; + + /* + * Walk the links to parse the full graph. Each channel will have + * one endpoint of the composite node. Start by parsing the + * composite node and parse the remote entities in turn. + * Each channel will register v4l2 async notifier to make the graph + * independent between the channels so we can the current channel + * in case of something wrong during graph parsing and continue with + * next channels. + */ + list_for_each_entry(chan, &vi->vi_chans, list) { + remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0); + if (!remote) + continue; + + ret = tegra_vi_graph_parse_one(chan, remote); + fwnode_handle_put(remote); + if (ret < 0 || list_empty(&chan->notifier.asd_list)) + continue; + + chan->notifier.ops = &tegra_vi_async_ops; + ret = v4l2_async_notifier_register(&vid->v4l2_dev, + &chan->notifier); + if (ret < 0) { + dev_err(vi->dev, + "failed to register channel %d notifier: %d\n", + chan->portno, ret); + v4l2_async_notifier_cleanup(&chan->notifier); + } + } + + return 0; +} + +void tegra_vi_graph_cleanup(struct tegra_vi *vi) +{ + struct tegra_vi_channel *chan; + + list_for_each_entry(chan, &vi->vi_chans, list) { + video_unregister_device(&chan->video); + mutex_lock(&chan->video_lock); + vb2_queue_release(&chan->queue); + mutex_unlock(&chan->video_lock); + v4l2_async_notifier_unregister(&chan->notifier); + v4l2_async_notifier_cleanup(&chan->notifier); + } +} + static int tegra_vi_init(struct host1x_client *client) { struct tegra_video_device *vid = dev_get_drvdata(client->host); @@ -922,13 +1471,14 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto free_chans; - } + else + ret = tegra_vi_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate vi channels: %d\n", ret); + goto free_chans; } ret = tegra_vi_channels_init(vi); @@ -937,6 +1487,12 @@ static int tegra_vi_init(struct host1x_client *client) vid->vi = vi; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_graph_init(vi); + if (ret < 0) + goto free_chans; + } + return 0; free_chans: @@ -950,6 +1506,8 @@ static int tegra_vi_init(struct host1x_client *client) static int tegra_vi_exit(struct host1x_client *client) { + struct tegra_vi *vi = host1x_client_to_vi(client); + /* * Do not cleanup the channels here as application might still be * holding video device nodes. Channels cleanup will happen during @@ -957,6 +1515,9 @@ static int tegra_vi_exit(struct host1x_client *client) * device nodes are released. */ + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_vi_graph_cleanup(vi); + return 0; } diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index 6272c9a..98f6d575 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,19 @@ struct tegra_vi { }; /** + * struct tegra_vi_graph_entity - Entity in the video graph + * + * @asd: subdev asynchronous registration information + * @entity: media entity from the corresponding V4L2 subdev + * @subdev: V4L2 subdev + */ +struct tegra_vi_graph_entity { + struct v4l2_async_subdev asd; + struct media_entity *entity; + struct v4l2_subdev *subdev; +}; + +/** * struct tegra_vi_channel - Tegra video channel * * @list: list head for this entry @@ -138,10 +152,13 @@ struct tegra_vi { * @done_lock: protects the capture done queue list * * @portno: VI channel port number + * @of_node: device node of VI channel * * @ctrl_handler: V4L2 control handler of this video channel + * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats * @tpg_fmts_bitmap: a bitmap for supported TPG formats * @pg_mode: test pattern generator mode (disabled/direct/patch) + * @notifier: V4L2 asynchronous subdevs notifier */ struct tegra_vi_channel { struct list_head list; @@ -174,10 +191,14 @@ struct tegra_vi_channel { spinlock_t done_lock; unsigned char portno; + struct device_node *of_node; struct v4l2_ctrl_handler ctrl_handler; + DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); enum tegra_vi_pg_mode pg_mode; + + struct v4l2_async_notifier notifier; }; /** @@ -249,7 +270,7 @@ extern const struct tegra_vi_soc tegra210_vi_soc; #endif struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan); +tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor); int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); void tegra_channel_release_buffers(struct tegra_vi_channel *chan, enum vb2_buffer_state state); From patchwork Wed Jun 10 06:02:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64409 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmk-006p3M-Ps; Wed, 10 Jun 2020 06:00:28 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726455AbgFJGD6 (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:58 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11236 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726273AbgFJGCw (ORCPT ); Wed, 10 Jun 2020 02:02:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:51 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:50 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:50 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:50 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 12/18] media: tegra-video: Add support for selection ioctl ops Date: Tue, 9 Jun 2020 23:02:34 -0700 Message-ID: <1591768960-31648-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768879; bh=DdvP/XW9hYASnGAPIhOT29pXz3T5UjbPtLN0juCmevk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XWXDYye7s7Ufn+DmC7r+uZ96qg/VwSsMYQYrQ9FoyGhfjMPjTz8UZ4dJiBBk6TaNG xyI0oUvsqovGo0qYzpCpN/+CAkxwwlSeC3xDJUnlz1zqW8pUx4EWU0vI6vJrzSqXea lx+hZa3KvYJ+ZszkIxcTphv8pejnEzBOta0OR3tlKqeIGvRC+1qmbmJUy1K6fmCSNe 453aVDaRLyhkx7pwli7BL0U2B7u2Re5X4T77AVUpKbns15ZCCPmAZoW2U4WW6zopnt YU4h9f383xptqhNkm/aZGZTJFBrvMugE/643FRoahPirlnLKVqAsaNTRJ0MR7F/zkH eVEwaT6FAMwCA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds selection v4l2 ioctl operations to allow configuring a selection rectangle in the sensor through the Tegra video device node. Some sensor drivers supporting crop uses try_crop rectangle from v4l2_subdev_pad_config during try format for computing binning. So with selection ops support, this patch also updates try format to use try crop rectangle either from subdev frame size enumeration or from subdev crop boundary. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 6f320c1..03def26 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -427,6 +427,13 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + struct v4l2_subdev_frame_size_enum fse = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = V4L2_SEL_TGT_CROP_BOUNDS, + }; int ret; subdev = tegra_channel_get_remote_subdev(chan, true); @@ -449,6 +456,24 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); + + /* + * Attempt to obtain the format size from subdev. + * If not available, try to get crop boundary from subdev. + */ + fse.code = fmtinfo->code; + ret = v4l2_subdev_call(subdev, pad, enum_frame_size, pad_cfg, &fse); + if (ret) { + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (ret) + return -EINVAL; + pad_cfg->try_crop.width = sdsel.r.width; + pad_cfg->try_crop.height = sdsel.r.height; + } else { + pad_cfg->try_crop.width = fse.max_width; + pad_cfg->try_crop.height = fse.max_height; + } + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); if (ret < 0) return ret; @@ -540,6 +565,85 @@ static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) return 0; } +static int tegra_channel_g_selection(struct file *file, void *priv, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + }; + int ret; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + /* + * Try the get selection operation and fallback to get format if not + * implemented. + */ + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); + if (!ret) + sel->r = sdsel.r; + if (ret != -ENOIOCTLCMD) + return ret; + + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret < 0) + return ret; + + sel->r.left = 0; + sel->r.top = 0; + sel->r.width = fmt.format.width; + sel->r.height = fmt.format.height; + + return 0; +} + +static int tegra_channel_s_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + int ret; + struct v4l2_subdev_selection sdsel = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .target = sel->target, + .flags = sel->flags, + .r = sel->r, + }; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return -ENOTTY; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vb2_is_busy(&chan->queue)) + return -EBUSY; + + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, set_selection, NULL, &sdsel); + if (!ret) { + sel->r = sdsel.r; + /* + * Subdev active format resolution may have changed during + * set selection operation. So, update channel format to + * the sub-device active format. + */ + return tegra_channel_set_subdev_active_fmt(chan); + } + + return ret; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { @@ -597,6 +701,8 @@ static const struct v4l2_ioctl_ops tegra_channel_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_g_selection = tegra_channel_g_selection, + .vidioc_s_selection = tegra_channel_s_selection, }; /* From patchwork Wed Jun 10 06:02:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64407 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmg-006p2i-6T; Wed, 10 Jun 2020 06:00:22 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726485AbgFJGD7 (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:59 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6104 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726275AbgFJGCw (ORCPT ); Wed, 10 Jun 2020 02:02:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:06 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:51 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:51 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:51 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 13/18] gpu: host1x: mipi: Add of_tegra_mipi_request() API Date: Tue, 9 Jun 2020 23:02:35 -0700 Message-ID: <1591768960-31648-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768926; bh=qd5ZedoXJM6zCreLe65FRGR8l6so02mvB+u6w942LLM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dnismLbIeUjyT/UE4bEjAB6TfGtTrBB8Vd7yNwEQYVo4azSGukxYMHJerqsxMlA45 wLLKLVb7s9hVuGVcuR37tglygJjIgevZuVKmIvDIQzSPAMWUnHzb+EDXbcOHZtUzVp AQPIcltO0DLfdixvfbUfU2JpDafnGEmR6T5E+sJ1ypp+TuCom/CSDcHOpNn7IfYKck trR3iP1w6j+pxgb02f0lflSjHYPPq02bAJec/bVoEFcAoYF2KFUnA2MDsEU4KBtG5y pI31gIyEo8xJ+LIPVGjLlhTjXzya3o/7jvrbzBKemnDAa/kA5ZpXLAEM5k4FCS0RRI G5MmQEk+yrUzQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch adds an API of_tegra_mipi_request() to allow creating mipi device for specific device node rather than a device so Tegra CSI driver can use it for calibrating MIPI pads for each stream independently. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/host1x/mipi.c | 10 ++++++++-- include/linux/host1x.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e00809d..f51fe69 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -206,9 +206,9 @@ static int tegra_mipi_power_down(struct tegra_mipi *mipi) return 0; } -struct tegra_mipi_device *tegra_mipi_request(struct device *device) +struct tegra_mipi_device *of_tegra_mipi_request(struct device *device, + struct device_node *np) { - struct device_node *np = device->of_node; struct tegra_mipi_device *dev; struct of_phandle_args args; int err; @@ -252,6 +252,12 @@ struct tegra_mipi_device *tegra_mipi_request(struct device *device) of_node_put(args.np); return ERR_PTR(err); } +EXPORT_SYMBOL(of_tegra_mipi_request); + +struct tegra_mipi_device *tegra_mipi_request(struct device *device) +{ + return of_tegra_mipi_request(device, device->of_node); +} EXPORT_SYMBOL(tegra_mipi_request); void tegra_mipi_free(struct tegra_mipi_device *device) diff --git a/include/linux/host1x.h b/include/linux/host1x.h index c230b4e..a61ca52 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -325,6 +325,8 @@ int host1x_client_resume(struct host1x_client *client); struct tegra_mipi_device; +struct tegra_mipi_device *of_tegra_mipi_request(struct device *device, + struct device_node *np); struct tegra_mipi_device *tegra_mipi_request(struct device *device); void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); From patchwork Wed Jun 10 06:02:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64404 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmC-006p1k-S1; Wed, 10 Jun 2020 05:59:53 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726401AbgFJGDj (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:39 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11247 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726279AbgFJGCy (ORCPT ); Wed, 10 Jun 2020 02:02:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:52 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:52 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:52 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:52 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:51 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 14/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait Date: Tue, 9 Jun 2020 23:02:36 -0700 Message-ID: <1591768960-31648-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768881; bh=4ES5kAI2PqYLOuW0Im9Hz1dnAeW5Q4i+H7tHmdv9tVo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=E037ThJS7qicWEsMWvyN/ueFgwG4zQpBEo07RuddWKJ32kyJJ0rkb2WGoa1D9Xx3S aYYnrbQ5C3DxvzcEaK4o8IYsP9DzAgP6QJj/0vu7gSL1dLGv407/4ZYwYTsyG0uQz4 KWf+mdaWYqJ8JnvHIglMdYixDisYyR/XF986yG8HRzjkptct4cZ7L9uPeadAPGzPvV yIshu15lKPipChUSrC7cu30GqO9SsPAFoUNScf4gNuRWAw4GzXwPgmNAtu9fl8Qy5q JPtccvmr/83nkDj1GZOYRu0Dbig07SfMBAZWQKqvaDcF8hdmf+vZ4uzDx4ZqNwROSf k12s7xbWpFdIA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no SW can trigger MIPI pads calibration any time after power on but calibration results will be latched and applied to the pads by MIPI CAL unit only when the link is in LP-11 state and then status register will be updated. For CSI, trigger of pads calibration happen during CSI stream enable where CSI receiver is kept ready prior to sensor or CSI transmitter stream start. So, pads may not be in LP-11 at this time and waiting for the calibration to be done immediate after calibration start will result in timeout. This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() so triggering for calibration and waiting for it to complete can happen at different stages. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/drm/tegra/dsi.c | 7 ++++++- drivers/gpu/host1x/mipi.c | 23 +++++++++++++++++------ include/linux/host1x.h | 1 + 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 38beab9..814363f 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -670,6 +670,7 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { u32 value; + int ret; /* * XXX Is this still needed? The module reset is deasserted right @@ -693,7 +694,11 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - return tegra_mipi_calibrate(dsi->mipi); + ret = tegra_mipi_calibrate(dsi->mipi); + if (ret < 0) + return ret; + + return tegra_mipi_wait(dsi->mipi); } static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index f51fe69..a01df6a 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -299,22 +299,35 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) } EXPORT_SYMBOL(tegra_mipi_disable); -static int tegra_mipi_wait(struct tegra_mipi *mipi) +int tegra_mipi_wait(struct tegra_mipi_device *device) { + struct tegra_mipi *mipi = device->mipi; unsigned long timeout = jiffies + msecs_to_jiffies(250); u32 value; + int err; + + err = clk_enable(device->mipi->clk); + if (err < 0) + return err; + + mutex_lock(&device->mipi->lock); while (time_before(jiffies, timeout)) { value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && (value & MIPI_CAL_STATUS_DONE) != 0) - return 0; + goto done; usleep_range(10, 50); } - return -ETIMEDOUT; + err = -ETIMEDOUT; +done: + mutex_unlock(&device->mipi->lock); + clk_disable(device->mipi->clk); + return err; } +EXPORT_SYMBOL(tegra_mipi_wait); int tegra_mipi_calibrate(struct tegra_mipi_device *device) { @@ -380,12 +393,10 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) value |= MIPI_CAL_CTRL_START; tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); - err = tegra_mipi_wait(device->mipi); - mutex_unlock(&device->mipi->lock); clk_disable(device->mipi->clk); - return err; + return 0; } EXPORT_SYMBOL(tegra_mipi_calibrate); diff --git a/include/linux/host1x.h b/include/linux/host1x.h index a61ca52..dbad062 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -332,5 +332,6 @@ void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); int tegra_mipi_calibrate(struct tegra_mipi_device *device); +int tegra_mipi_wait(struct tegra_mipi_device *device); #endif From patchwork Wed Jun 10 06:02:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64408 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmh-006p2i-CD; Wed, 10 Jun 2020 06:00:24 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726474AbgFJGD6 (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:58 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10517 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726277AbgFJGCx (ORCPT ); Wed, 10 Jun 2020 02:02:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:39 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:53 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:52 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:52 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:52 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 15/18] media: tegra-video: Add CSI MIPI pads calibration Date: Tue, 9 Jun 2020 23:02:37 -0700 Message-ID: <1591768960-31648-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768959; bh=AWSdGho3B6opMA0Fsj5eNKNr921zMuFJ1SGjzzkoGx4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dWurmY7e/RIK7jLEzGvdkzDQTgwWXsvLr+DjO4v1sdCSmveULTytMCj6X0zCWetCW h4sXTIzz/XiwbO38V3PDe+NbwQJlI+MLbhAeEm+sz1d8ldCEvhS2rch/AaFuTQV+73 rNnVJSeSzGaiCfECSfL1SilJnKPP1CS1VX1td9n6EPUROezmSWe00WRdmylUhNwRzY PUQbAv8ZDXxWVZ/Dxdf0vy7STIXE3vlwtUxclMO4OqAohhKh1j5KpVKbC/1smJYNAr rB184zcSnWJMTijAAMQHSWRMgpSnYoyxlPzfQPoFqa2NW5+bJNXDl+/1Ozmk2T3WIs Dhnmq+5iNCGfg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no CSI MIPI pads need to be enabled and calibrated for capturing from the external sensor or transmitter. MIPI CAL unit calibrates MIPI pads pull-up, pull-down and termination impedances. Calibration is done by co-work of MIPI BIAS pad and MIPI CAL control unit. Triggering calibration start can happen any time after MIPI pads are enabled but calibration results will be latched and applied to MIPI pads by MIPI CAL unit only when the link is in LP11 state and then calibration status register gets updated. This patch enables CSI MIPI pads and calibrates them during streaming. Tegra CSI receiver is able to catch the very first clock transition. So, CSI receiver is always enabled prior to sensor streaming and trigger of calibration start is done during CSI subdev streaming and status of calibration is verified after sensor stream on. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 44 +++++++++++++++++++++++++++++++-- drivers/staging/media/tegra-video/csi.h | 2 ++ drivers/staging/media/tegra-video/vi.c | 18 ++++++++++++++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 14e9050..82e340a 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -249,15 +249,42 @@ static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) return ret; } + if (csi_chan->mipi) { + ret = tegra_mipi_enable(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to enable MIPI pads: %d\n", + ret); + goto rpm_put; + } + + /* + * CSI MIPI pads PULLUP, PULLDN and TERM impedances + * need to be calibrated after power on. + * So, trigger the calibration start here and results + * will be latched and applied to the pads when link is + * in LP11 state during start of sensor streaming. + */ + tegra_mipi_calibrate(csi_chan->mipi); + } + ret = csi->ops->csi_start_streaming(csi_chan); if (ret < 0) - goto rpm_put; + goto disable_mipi; return 0; } csi->ops->csi_stop_streaming(csi_chan); +disable_mipi: + if (csi_chan->mipi) { + ret = tegra_mipi_disable(csi_chan->mipi); + if (ret < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", ret); + } + rpm_put: pm_runtime_put(csi->dev); return ret; @@ -291,6 +318,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; + int ret = 0; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -309,7 +337,16 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; } - return 0; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + chan->mipi = of_tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret = PTR_ERR(chan->mipi); + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } + + return ret; } static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) @@ -473,6 +510,9 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) struct tegra_csi_channel *chan, *tmp; list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { + if (chan->mipi) + tegra_mipi_free(chan->mipi); + subdev = &chan->subdev; if (subdev->dev) { if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index b7b754a..0e5a537 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -51,6 +51,7 @@ struct tegra_csi; * @framerate: active framerate for TPG * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format + * @mipi: mipi device for corresponding csi channel pads */ struct tegra_csi_channel { struct list_head list; @@ -66,6 +67,7 @@ struct tegra_csi_channel { unsigned int framerate; unsigned int h_blank; unsigned int v_blank; + struct tegra_mipi_device *mipi; }; /** diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 03def26..337a19f 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -187,6 +187,7 @@ tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor) int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { struct v4l2_subdev *subdev; + struct tegra_csi_channel *csi_chan; int ret; /* stream CSI */ @@ -198,11 +199,28 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) return 0; + if (on) + csi_chan = v4l2_get_subdevdata(subdev); + subdev = tegra_channel_get_remote_subdev(chan, on); ret = v4l2_subdev_call(subdev, video, s_stream, on); if (on && ret < 0 && ret != -ENOIOCTLCMD) return ret; + /* + * CSI subdev stream on triggers start of MIPI pads calibration. + * Calibration results are latched and applied to the pads when + * link is in LP11 state which will hapen during sensor streaming. + * So, wait for calibration to complete here. + */ + if (on && csi_chan->mipi) { + ret = tegra_mipi_wait(csi_chan->mipi); + if (ret < 0) + dev_err(csi_chan->csi->dev, + "MIPI calibration failed: %d\n", ret); + return ret; + } + return 0; } From patchwork Wed Jun 10 06:02:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64403 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmB-006p1k-7E; Wed, 10 Jun 2020 05:59:52 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbgFJGDj (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:39 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6113 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726112AbgFJGCy (ORCPT ); Wed, 10 Jun 2020 02:02:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:53 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:53 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:53 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:53 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 16/18] media: tegra-video: Compute settle times based on the clock rate Date: Tue, 9 Jun 2020 23:02:38 -0700 Message-ID: <1591768960-31648-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768928; bh=VN6FVs1l4xS3sEzG6E2hvQ8WglAefjSdk4oyRtTRSVY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Tv2WFcOFfKcbl9IVrO4IWAN9It1FicVs2C8hmMg5AabxRrFFEOraCzzFo9aZ5hB6w dmeuOa4enghNO4scnCuy+Wq4r6nxgXtl+7EPLrYRMkas0ZAL37WMg/Dj44undrsSa5 1XRWQPykd6WDHxBujpJWWldkmTsb5SlQdWuEHUwcRE4GsDyukkib9BPKq5OR4fjjy8 dHSQgChD1JkUbDfBCTckVRpMMCYUYQq9uDdVtiaGLo56HNlBHGLF6PBrtr8NyB0m44 Ae0ICBqORPLC7VJlqdSrIAh3rL47YfqzsT8Q2jtWmdPDbtVew69WiC9Kc7J6mps/Ms z4NYx4SDtdEQQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Settle time determines the number of cil clock cyles to wait after LP00 when moving from LP to HS. This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil clock rate and pixel rate from the sensor and programs them during streaming. T-CLK-SETTLE time is the interval during which receiver will ignore any HS transitions on clock lane starting from the beginning of T-CLK-PREPARE. T-HS-SETTLE time is the interval during which recevier will ignore any HS transitions on data lane starting from the beginning of T-HS-PREPARE. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 55 ++++++++++++++++++++++++++++ drivers/staging/media/tegra-video/csi.h | 5 +++ drivers/staging/media/tegra-video/tegra210.c | 17 ++++++++- 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 82e340a..0f4d815 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -16,6 +16,8 @@ #include "csi.h" #include "video.h" +#define MHZ 1000000 + static inline struct tegra_csi * host1x_client_to_csi(struct host1x_client *client) { @@ -232,6 +234,59 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } +static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) +{ + struct tegra_vi_channel *chan; + struct v4l2_subdev *src_subdev; + struct v4l2_ctrl *ctrl; + + chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); + src_subdev = tegra_channel_get_remote_subdev(chan, true); + ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); + if (ctrl) + return v4l2_ctrl_g_ctrl_int64(ctrl); + + return 0; +} + +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time) +{ + struct tegra_csi *csi = csi_chan->csi; + unsigned int cil_clk_mhz; + unsigned int pix_clk_mhz; + int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + + cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; + pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; + + /* + * CLK Settle time is the interval during which HS receiver should + * ignore any clock lane HS transitions, starting from the beginning + * of T-CLK-PREPARE. + * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns + * + * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns + * midpoint = 197.5 ns + */ + *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; + + /* + * THS Settle time is the interval during which HS receiver should + * ignore any data lane HS transitions, starting from the beginning + * of THS-PREPARE. + * + * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI + * and 145ns+10UI. + * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI + * midpoint = 115ns + 8UI + */ + if (pix_clk_mhz) + *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz + / (2 * pix_clk_mhz) - 5000) / 1000; +} + static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 0e5a537..a52c7da1 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -52,6 +52,7 @@ struct tegra_csi; * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format * @mipi: mipi device for corresponding csi channel pads + * @pixel_rate: active pixel rate from the sensor on this channel */ struct tegra_csi_channel { struct list_head list; @@ -68,6 +69,7 @@ struct tegra_csi_channel { unsigned int h_blank; unsigned int v_blank; struct tegra_mipi_device *mipi; + unsigned int pixel_rate; }; /** @@ -148,4 +150,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; #endif void tegra_csi_error_recover(struct v4l2_subdev *subdev); +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 4f5080a..bcc0492 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -7,6 +7,7 @@ * This source file contains Tegra210 supported video formats, * VI and CSI SoC specific data, operations and registers accessors. */ +#include #include #include #include @@ -98,6 +99,8 @@ #define BRICK_CLOCK_B_4X (0x2 << 16) #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 +#define CLK_SETTLE_MASK GENMASK(13, 8) +#define THS_SETTLE_MASK GENMASK(5, 0) #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c #define TEGRA_CSI_CIL_STATUS 0x010 #define TEGRA_CSI_CILX_STATUS 0x014 @@ -770,8 +773,14 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) { struct tegra_csi *csi = csi_chan->csi; unsigned int portno = csi_chan->csi_port_num; + u8 clk_settle_time = 0; + u8 ths_settle_time = 10; u32 val; + if (!csi_chan->pg_mode) + tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + &ths_settle_time); + csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); /* clean up status */ @@ -782,7 +791,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) /* CIL PHY registers setup */ cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); - cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); /* * The CSI unit provides for connection of up to six cameras in @@ -801,7 +812,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) BRICK_CLOCK_A_4X); cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); - cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); } else { From patchwork Wed Jun 10 06:02:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64402 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitls-006p0Q-DO; Wed, 10 Jun 2020 05:59:32 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726367AbgFJGDa (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:30 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11256 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726280AbgFJGC5 (ORCPT ); Wed, 10 Jun 2020 02:02:57 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:54 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Jun 2020 23:02:54 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:53 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:53 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:53 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 17/18] arm64: tegra: jetson-tx1: Add camera supplies Date: Tue, 9 Jun 2020 23:02:39 -0700 Message-ID: <1591768960-31648-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768882; bh=znV249BjYdNn7v2dlbamoh4NYD4Ln2Jw53yQHV98OCI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=U+bufTyGxeZZq+0bzplTJ2AIZQ47lCPR4aro1JIT/l3vC3/9FuW3NZmP4kNnFGJ8N h++CmUN6qMesNXfxY24aFmDVMLVvYk2YlenD/6KcNBXhtWUbA7yL0XNfiRqsjNqiM3 dRTVLciclWXclOzdO2Vcal++QSLAMLK2izQ96fVM7lsgWpoztnTk7WA4w3lSsSktf9 Asd0cRJIYtDkSTAfPx9zlJVkadeaJYz/iuiKnw5dgcAmL/Tas/6CBLorUrNfDaX017 DMosSZd2psfQxVMSVTp7qoXQREDxBqgWg2en83ocE/X1KPCNAfMFjs3FR/IkCJjduw FXnSzBV5HlWBw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Jetson TX1 development board has a camera expansion connector which has 2V8, 1V8 and 1V2 supplies to power up the camera sensor on the supported camera modules. Camera module designed as per Jetson TX1 camera expansion connector may use these supplies for camera sensor avdd 2V8, digital core 1V8, and digital interface 1V2 voltages. These supplies are from fixed regulators on TX1 carrier board with enable control signals from I2C GPIO expanders. This patch adds these camera supplies to Jetson TX1 device tree to allow using these when a camera module is used. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index b57d837..5e24d7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1323,6 +1323,14 @@ #gpio-cells = <2>; gpio-controller; }; + + exp2: gpio@77 { + compatible = "ti,tca9539"; + reg = <0x77>; + + #gpio-cells = <2>; + gpio-controller; + }; }; /* HDMI DDC */ @@ -1667,6 +1675,39 @@ enable-active-high; vin-supply = <&vdd_5v0_sys>; }; + + vdd_cam_1v2: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vdd-cam-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&exp2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_cam_2v8: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "vdd-cam-2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&exp1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_cam_1v8: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "vdd-cam-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&exp2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; }; gpio-keys { From patchwork Wed Jun 10 06:02:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 64405 X-Patchwork-Delegate: hverkuil@xs4all.nl Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jitmI-006p1k-5i; Wed, 10 Jun 2020 05:59:58 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726385AbgFJGDi (ORCPT + 1 other); Wed, 10 Jun 2020 02:03:38 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10526 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726281AbgFJGCz (ORCPT ); Wed, 10 Jun 2020 02:02:55 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:02:41 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:54 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:54 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:54 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:54 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 23:02:54 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 18/18] arm64: tegra: Enable Tegra VI CSI support for Jetson Nano Date: Tue, 9 Jun 2020 23:02:40 -0700 Message-ID: <1591768960-31648-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768961; bh=SY37x9I8FIxsGnkaaa43HhEyCfrzG7BzBuiyswO6da0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=KM98G/ZhHUWpM6/3wXmNXy4wHS6k4ktzv4URA5innnyBkznz9TkYNzel7zIxowseh q71e4DjbyDjHplm5Ve/R0QzIZzeWO5FqE87IojflwoCQgSTAlJbGqufGne7ILWJ8zb DBuH5i0R1gWiOOoWZwdG4PUt51SazrWJo1rR7lWhhNidVwdkCO0zXmaMqd9frxi/dv dZ5lKj/UdNQwq+ejqCZIIUlLOEKI+PFprSLRICd8fawoHRjq4U0gU0bbo/DNNjLaHi mE6RaYQJvXvcj1oLBk8lHPt+83EWmDuD7i7nFVl94f+WaRP6dJwYbB0GMboS0KGDFu ErMkAs7D+sRCw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no This patch enables VI and CSI in device tree for Jetson Nano. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9bc52fd..eab5c5e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -64,6 +64,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_sys_1v2>; + + csi@838 { + status = "okay"; + }; + }; + sor@54540000 { status = "okay";