From patchwork Mon Aug 12 07:08:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "jackson.lee" X-Patchwork-Id: 103405 X-Patchwork-Delegate: sebastian.fricke@collabora.com Received: from am.mirrors.kernel.org ([147.75.80.249]) by linuxtv.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sdPAu-0004WQ-0L for patchwork@linuxtv.org; Mon, 12 Aug 2024 07:09:05 +0000 Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 1E11F1F22939 for ; Mon, 12 Aug 2024 07:09:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DA46215C13A; Mon, 12 Aug 2024 07:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="JCyQTjSk" X-Original-To: linux-media@vger.kernel.org Received: from SLXP216CU001.outbound.protection.outlook.com (mail-koreacentralazon11021080.outbound.protection.outlook.com [40.107.42.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12169152790; Mon, 12 Aug 2024 07:08:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.42.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446527; cv=fail; b=KIWZ86aKs5jj8Ue/e3ZkRH3qmzS772OWBVzpWbAEMG/kjHU0Bk+sALwScSnmEESeqLl0Ot5r/We7IXZA7bXnGaxf96tgRB503F6LQtEeNzcfuEQe0klGr5CMFVcJnjuesyoevZ6MT8NtZK/bTx2c8vapFrsDISx53d4kz1CAf1U= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446527; c=relaxed/simple; bh=kSDctqTnLEaMTcIwVIkXuc+h23dPmZ7zEJMLWdW9WEs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=q8AMi5Xl3OUty8fUwknLz7zJGObV/odvgTETmWj5Jd9oznOJCaJce1wjbhNTeljrW4nCgkXnCt5cAV+17WaeGWpDOAgJN8g/VrLWmkfHa2Nit4yMhCHZsEFj9qy6YgEHlbkAHcAJcJm4IvSvUvQhCRzCX+uL7ITzBLOd/CD1SOk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=JCyQTjSk; arc=fail smtp.client-ip=40.107.42.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IjOPLkhL34oLvfSyainq6K+alrJq05vnIbMTyWfcKqRrCR+ao9zIve1LEEvoLHIEaQb66U4/QexB3H7TRBvDuqz6LpJBEgCfzDlfShPKPlrLHsStm4Gg9VMQTYSzPtqiLZ4WDgY+Ry0Ov+TsmLtshEE2CXUwv8shXN1m6c/Rd9H68HgQJBoB08NGUjXOgS2/9hWh6N+tqSogiD1Gw9PfgSKATIBjRZZ8f4+2lQ7h1tZj133izwnfq5I77c9JMGnzjTmlo+SsDZMQMAc3e6yJ0arQQaBC0DvrQU2DKU7KoMhe4pjfSiGrRgG5pE2YmCynI0DHABYmuGl2bN13o/mgpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UWbNLWskET9h61KXYtOCGImr7d5KzHGfun3x8NvAomQ=; b=qZh8CBv5r3+kqp1I7DHrUuHhEPezutK4lMTFsfLY6vwxNw54XUlDLEqUumNgJn5gK9AZsUSVnnaok0NYQOmCYQWlIvGMqkr+Sg/Y1EYqCILrcAc9Y41IGQZ+3e/+NtL0nnSGcNbcKlieyn4AtUiWMrOg+K5ngrEE65jQ4vn0BDOx/+wPrF0xK0kndRTyA/AjcuInG4+7zhlCKz/FkQfESuxhR1F7MuHIS8xOW/sywgnqgIMOZZe8Sg6LkpKLa7e6Y05ooBc/O2hcvoCHlPMPdvDRGlt33A0eDTvJmWmpK6sHZWi5U3al5kfxBavyPG8smNq0jjLNpOWSy4jcstSexg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UWbNLWskET9h61KXYtOCGImr7d5KzHGfun3x8NvAomQ=; b=JCyQTjSkDQFKhNsrRDiM7yZc6qXVh8a6OCP96yzTwqdiF6DWcsblyT5DFkoDfyeBdlcxETd7Q7prsGDHggMPwbSOmpSm+vnOVH8cP4ECtIoGcprKPklt+TcOyQDea3/l+oiTY2t9pPQJkanjU/eVCPmeQytSnZnWAYOhk1EyF3U= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) by SL2P216MB1530.KORP216.PROD.OUTLOOK.COM (2603:1096:101:33::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 07:08:39 +0000 Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b]) by SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b%7]) with mapi id 15.20.7849.019; Mon, 12 Aug 2024 07:08:39 +0000 From: "Jackson.lee" To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipsnmedia.com, Nicolas Dufresne Subject: [RESEND PATCH v7 1/4] media: chips-media: wave5: Support SPS/PPS generation for each IDR Date: Mon, 12 Aug 2024 16:08:20 +0900 Message-Id: <20240812070823.125-2-jackson.lee@chipsnmedia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812070823.125-1-jackson.lee@chipsnmedia.com> References: <20240812070823.125-1-jackson.lee@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0154.KORP216.PROD.OUTLOOK.COM (2603:1096:101:35::18) To SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SE1P216MB1303:EE_|SL2P216MB1530:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d12b3e3-dbc2-44f5-e21c-08dcba9d975a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: DAJp01uaWpVAZwAr508ayXNkopfRBnKZnLHvHzFX6EHTkCySmz4rdM21wH49/b2lb8dgeIiCiCCaBcFLS637PUTTV6x4ELQSZH3g14lFb2KRoqmZ/wUlXAPTIAJ/xV0SxyS5QO5G22RzMp77+5RAf5jVz3zqW7htdGQEY/SoH3fLMnxqNiKn4YRyfTQLCQuT0VW3DCzXHgsiHIfe5j6ahAbDqHJWurdC53cs7PHpqwJ0pq+bTTV4HjX+/ll1FPg1cSsIf3DT03yljnbB6VhRBydbelB0btXg17W4WF5VYW6ulkilu/BqXsKVWyEkVjAKAKEuQNQXE/f3GdKQGIhU3bKNXh1dv05hM+vl8m+w1VtXokEXmtmgc58ElJR1Zdf7i0NQ8NK6KZ4C8h8/X7ZZXf0khPuGNZ9EUBHjnssx6M8dISQd8/OcDFJTULqIdioggmrwmIWXGV6lQlKPYVPe48l/edSt0Lt1bxvuC8ps4jg9WD7eb8OkckxefCETqHe7DJmThAAIz1oUSQYU5ownj2pntJLyQO2BjPKxwNxVTlgD/VHkhcav8veuk1SlpBXKqbBq0iA8jtiRbk/hjMFx4Hp0oKAvRCmOO+PJe0nHU70btWj/1ioP1cGia5RSD5DM+CFfZX1/hq7wyPgZQMTGDoe7FSWkbggURduEv7vK3YS9KHAIeEn9rm8X3dxYQngrxAbq8bWDdU3/ohuRGi8iAiF57KnkJR/IYZrWT3QASi6WN2O8Bf5Et6XZtREwLk4mGE55JOUWVixuG29VxclxyrqVQ9tsFdn/jw6NRMle+Kk9wk1N42+gUmNCvkJ1N9qPWHW3Z7VuBeF3tVE1Pw2JKSBDTr36TxpC7lpKISwDHuGSaz+djRDqZuJsLHUgDOGWkj39FLlh7NFVsonAcbgVLVR8xanLAVrVbp24L0tXeVl8IiHvWFPuL19DOD7RT1sjr3N/PKypsmu7BmfEUC9/RD2ZiXYrzuEKDvBsvwOZyEy0PIvBYR3/0c8xBERffGOC+jCqbQH9qERZSzgq0FdAhVNrIqlDRZD6GPUgA0ABdmAN7CTW5mv/H4s0ZsIRiTfea2d4GiWjsAFBTH+gMtGjj+UKKkyj+t1DoBks5UOsGMZ0kHKORJ22mQ1orkxXxXRyUwrP0k8UAGUeYxrJDcJ9Kkz/o+2CPgezofeGA1X+PLYHJLQPXQ8OILE90JLSJTbjVaB8w3CVxkMqBoCLeDR5XveUL8NDRrPn0ehAlM3oZg/PXpvnIBGUOUrMkB8b2F/S9+vrolo1TrCXZRO5hXQ/z20N0V+F+ztQGdThybS1NnLMj76odOMhtB8LbxvwvHGRXj1pnCoGBIwVtn6wR5QFbm/Eni6TWc2M4bFyksrrmNwaJcq3tayCSU9JpI3dycT507ALvKLOV6wUAxDPUH9Wug== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SE1P216MB1303.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(52116014)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hlkJrfIOlqDhICXjXNP5U8dJT6Wyh3fghU0/ijvAwmzhYVzswBTX6+2bAazHKAi7a8eTWbZug7vEmYojGCC+Nt7uYhiARkKJP/lO2wxUfXp0fJDorESJw5gf06N4CGJj45OZI6M32Whm12nsMhIVo1GwkxsHQGH3C+9FeKWKK9+wZwQ2XCo89o3BnTVq3AeCKy/Inx07CNR7vlT+o+5JaMIbhO6A0jl4AuGYUvREF+41agujAbroloHJiy9A+Xa6AzSzoz0QtHpBUO4DEQX2c/GP2+UoeuoKB7GEu7oBFfzbhSUhbg7C85+4cPNMAwYyJHFhnQLzsbDQqFMLRjnM1H+taz303G42PCVsNASQIA9UO31Ly7gb7Y9rYHI6PlCLWB4p8rBIylHtkdkiutlYX32h3/XixQD75EoQgKG9Xfr5ojt8mQG3Cy0HY6TFJkdImumPcvWWtBA9307sPGx1stOGEqgsjjEJJW3m+QmCbRD8hSHV9cULOw0TUq3k5n4a1pC3qZJUB3TjsiHu6zkF4vwa2zJ/dI4e4Uwk2JPv40MKy6e+h2MKEl9vqTgUYbqAuWLy4oOFN8mfMzJmyfzTRF4CW3BR3IV1k6hERAcRoFQF3K9tSFow2SO44x+2KLZDunEEtQB6VC3/q4VEd2QF4YMrORKxFKF27h7Kpc8Wy9D1TOWygQe8Osz8Wf5Aj8OeibkOG+BJu8Uvswnl0Pq05fUbj0MXk2lNIOprNDNKAfre/Rn7D8ZamU4sAWT106ceMRtVktkBwc1Jd+IUrDrtAid7VJ9B8Zd0zY1xnIp+HnQlfprhJARBefcazTR6DLkw64JVIhk16mhh0V0IooA+D2PN3UHYPPqvmQWQQInvdej+v2CTkcIoPj1c5bY6QircF6SWZSQBl+wl1e4kbOAPW2GY5M366aTjvkUeTCgBysFGOczCXOQHv8J4WByLVx+vNSC2GQ8+jjtDZen7uZFqWf45YegYOW4KpvSvXLxJ7j5CqbC4hZDjFDWfR/nUGS8Neoi32O9lRJCxM43mrQQTBXSIQUwYXpEac0zlSCOU85JJkGr7FylKB3uprOcr+z0I+LmFUaROazmKZQYcFW4x1v5yMRhyjEzMBm9wWTb6wJZp4veaChy6LAzO53ujyn72VPcsATklOVet5eGae/yj0Iz/lFaJ2ZipGNVOpJV7+jaQpirdS+TvGzzOnw+KMIE/J+ctPDB41W4PJH301YXxAA426CBSfhNsxehiYgB9Sapxcm6M/PsWgpNjO17zTQ8GqwWWk8BRzarHjKXJ3IQ88MJbY1KYuubxGb6JZKFe1SnroY4ZUSUrc5Pjs4wduox4L9TQdit0GTtgo9CnzlRwZYyFBhNbtGsQ/PGuooZoIjWaIg5LBu5NLeddH58PXxMnTXtczd5/sTuDc5+6NTKcbAteec/9T4nudWhkFtZC3m8PoHXI8nkGVlihiT+eyjpqE9L/VdP8Von8sDfyUCDjMS4LJHlNfik/dS/iP2GaUnvpqYwTuzyCnTmJ0OeGVHCrgWqQ2PjpWZFqRIFRcBbOYLcQgSrnHcgrULhp1wXyU5E5cHV1L4zwaU4KbOrQI1cjWeMzwOrkOtrLiLesEQ9Gcw== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d12b3e3-dbc2-44f5-e21c-08dcba9d975a X-MS-Exchange-CrossTenant-AuthSource: SE1P216MB1303.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 07:08:39.2770 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: saglZGyhyMzJuYLLKS73HdSUm83vhChwOWdKHmHX8E1DsJgzrraNtk1oI70SE0mUxEsH4clfIRlw4ufkN4yYSArOg42zG39bGMA8xKzvuaQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB1530 X-LSpam-Score: -6.3 (------) X-LSpam-Report: No, score=-6.3 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DMARC_MISSING=0.001,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_VALIDITY_CERTIFIED=-3,RCVD_IN_VALIDITY_RPBL=1.31,RCVD_IN_VALIDITY_SAFE=-2,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=ham autolearn_force=no Provide a control to toggle (0 = off / 1 = on), whether the SPS and PPS are generated for every IDR. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-hw.c | 26 +++++++++++++++---- .../chips-media/wave5/wave5-vpu-enc.c | 7 +++++ .../platform/chips-media/wave5/wave5-vpuapi.h | 1 + 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index c89aafabc742..2a98bab446d0 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -23,6 +23,15 @@ #define W521_FEATURE_AVC_ENCODER BIT(1) #define W521_FEATURE_HEVC_ENCODER BIT(0) +#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff +#define ENC_AVC_INTRA_PERIOD_SHIFT 6 +#define ENC_AVC_IDR_PERIOD_SHIFT 17 +#define ENC_AVC_FORCED_IDR_HEADER_SHIFT 28 + +#define ENC_HEVC_INTRA_QP_SHIFT 3 +#define ENC_HEVC_FORCED_IDR_HEADER_SHIFT 9 +#define ENC_HEVC_INTRA_PERIOD_SHIFT 16 + /* Decoder support fields */ #define W521_FEATURE_AVC_DECODER BIT(3) #define W521_FEATURE_HEVC_DECODER BIT(2) @@ -35,7 +44,7 @@ #define REMAP_CTRL_MAX_SIZE_BITS ((W5_REMAP_MAX_SIZE >> 12) & 0x1ff) #define REMAP_CTRL_REGISTER_VALUE(index) ( \ - (BIT(31) | (index << 12) | BIT(11) | REMAP_CTRL_MAX_SIZE_BITS) \ + (BIT(31) | ((index) << 12) | BIT(11) | REMAP_CTRL_MAX_SIZE_BITS)\ ) #define FASTIO_ADDRESS_MASK GENMASK(15, 0) @@ -1772,12 +1781,19 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) if (inst->std == W_AVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | - ((p_param->intra_period & 0x7ff) << 6) | - ((p_param->avc_idr_period & 0x7ff) << 17)); + ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) + << ENC_AVC_INTRA_PERIOD_SHIFT) | + ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) + << ENC_AVC_IDR_PERIOD_SHIFT) | + (p_param->forced_idr_header_enable + << ENC_AVC_FORCED_IDR_HEADER_SHIFT)); else if (inst->std == W_HEVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, - p_param->decoding_refresh_type | (p_param->intra_qp << 3) | - (p_param->intra_period << 16)); + p_param->decoding_refresh_type | + (p_param->intra_qp << ENC_HEVC_INTRA_QP_SHIFT) | + (p_param->forced_idr_header_enable + << ENC_HEVC_FORCED_IDR_HEADER_SHIFT) | + (p_param->intra_period << ENC_HEVC_INTRA_PERIOD_SHIFT)); reg_val = (p_param->rdo_skip << 2) | (p_param->lambda_scaling_enable << 3) | diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 3e35a05c2d8d..b731decbfda6 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -1061,6 +1061,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: inst->enc_param.entropy_coding_mode = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: + inst->enc_param.forced_idr_header_enable = ctrl->val; + break; case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: break; default: @@ -1219,6 +1222,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, else open_param->wave_param.intra_refresh_arg = num_ctu_row; } + open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable; } static int initialize_sequence(struct vpu_instance *inst) @@ -1701,6 +1705,9 @@ static int wave5_vpu_open_enc(struct file *filp) 0, 1, 1, 0); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR, + 0, 1, 1, 0); if (v4l2_ctrl_hdl->error) { ret = -ENODEV; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index d2370511faf8..45615c15beca 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -568,6 +568,7 @@ struct enc_wave_param { u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */ u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */ u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ + u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */ }; struct enc_open_param { From patchwork Mon Aug 12 07:08:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "jackson.lee" X-Patchwork-Id: 103406 X-Patchwork-Delegate: sebastian.fricke@collabora.com Received: from am.mirrors.kernel.org ([147.75.80.249]) by linuxtv.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sdPB9-0004Yq-2c for patchwork@linuxtv.org; Mon, 12 Aug 2024 07:09:20 +0000 Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id A2DA71F211DC for ; Mon, 12 Aug 2024 07:09:17 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2561C165F01; Mon, 12 Aug 2024 07:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="ULORrAst" X-Original-To: linux-media@vger.kernel.org Received: from SLXP216CU001.outbound.protection.outlook.com (mail-koreacentralazon11021080.outbound.protection.outlook.com [40.107.42.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1F7C15886B; Mon, 12 Aug 2024 07:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.42.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446529; cv=fail; b=L1YaY6XuSUJMfG6DvKcYywr6rBV3y44DCKZZpIWFIPzlmNTGOITxBxATMYXWfONSJbcPyFzfXXSDmsiyI4Z8x8T0eKd7B4W5uukwBedeLYXTY4RzlIHacd5ObnNbxFEKXMf06/eGit5g49/0dSY3TYrJFvhRf8WhtDIrNuMavN0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446529; c=relaxed/simple; bh=1gH8Kst5AyvyREmhJnzJ4WA7ZLdac2yMvVZzwSm6PP4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=uB3O9TwngrN5odCwZjRESN8lJLpKyK4JrOl5HLZFw9wng3RTL0olwZT7L3lYM2QJB8hTGivpK6mHH2XPAWgAi4MbrHd2y4KYGgS0JKrRo7flqgal5WJY9FekpcZd588NC0Iw68cad5PMp+f9IwvDyQsLBZ2mlK0RLzokTElX5x4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=ULORrAst; arc=fail smtp.client-ip=40.107.42.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uhfPT/fGEvPFEAi9yrP+YlKkdAyFEsuRXeeNroJPRlLL3+ooZ3asULURwIHgMyyCvp3OdcU1GHfrP0gCig7B0EQYEadtEir2k/n/TCScJTtcr+8CwOf+xNVO3aHT6kUmHDisYIiZ6SrW7l3UzM4608e+GAKM44Bf7Mn/KWrTcfyTru2LStDRUlROWu3DnbTU11esl3Ku/ZsbPzryDn5BTGoGkoVc2B2s174FAByNJ8mtP1T2466VV71wRj3eEf3Q0paFj8QXecomM97J3gVaiPgv0JzXTKpsLL706jthDH45YdG4NibovCoS5ngbIVIgI2iYtXydzmsSkoYbmKhVMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EsuiMHgkIfdA/t5ukV023GxxCFgVF8UHfqk1OSNTkb4=; b=DbVqyvucTYAEV5Q+IBK8X8zhX9lp4bzPmYAi7xxGFIgK8t3E/oe4vDaI+MUi2W5m8ilK84LoRizdH8xHEm+Nwx83lisZMfHExnyg12gLhEVFizCuJBL0nnAvtOddE7jvYPNQQ6QUuItMP50cHDPIHCtyVFDj+f8+DbCFz80IJHaxTe055s33RqMz1kfEKl16RAV9MqKI9vBhYJdJ6iD5i1NLzlAhxJSLdQ/JLvTs17MPfuGPyvZkZM6/mjoHDG7rAH80fFk296gy5ZQ3GHHYMw7pshcXuHdByFZyJY88v7/mhgFWQAcqEV0YAKpwN4it2RBM/bEbg8qCtJX1Zaa2AA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EsuiMHgkIfdA/t5ukV023GxxCFgVF8UHfqk1OSNTkb4=; b=ULORrAstXNi3kpWhF1rhMmG4gOJ3NCLdw+3XHrcbxYisehlsxkwje/drV8nVIGJIjHrEKDjzw9aN8dDeSxb0BUbxWLTAU55LbyUuu9QBkBtY1kAv8jUw4a9HkXr4KBDsHBQz/Ll5qRiEZiIkW8sNIGAYJ6NM7hdXuVdcqrf1AyE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) by SL2P216MB1530.KORP216.PROD.OUTLOOK.COM (2603:1096:101:33::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 07:08:39 +0000 Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b]) by SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b%7]) with mapi id 15.20.7849.019; Mon, 12 Aug 2024 07:08:39 +0000 From: "Jackson.lee" To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipsnmedia.com, Nicolas Dufresne Subject: [RESEND PATCH v7 2/4] media: chips-media: wave5: Support runtime suspend/resume Date: Mon, 12 Aug 2024 16:08:21 +0900 Message-Id: <20240812070823.125-3-jackson.lee@chipsnmedia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812070823.125-1-jackson.lee@chipsnmedia.com> References: <20240812070823.125-1-jackson.lee@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0154.KORP216.PROD.OUTLOOK.COM (2603:1096:101:35::18) To SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SE1P216MB1303:EE_|SL2P216MB1530:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ce200ae-d417-495e-7e1b-08dcba9d9783 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: ivzttITxAecFrZUMcwUoCa7erS16i8ycK2zH2jaGIiS1yNdTnJsJkQZsvKGQOpNbNlXL4RtazGL0NVaXoxz8efNl1pln97mTpwqy+sUavWJvNlxRuyuhLLBpUEs5XHsq0H2eHvjXtL76eSG7dVzuJodzbZJbITxN5yfJeiw0MZo9sbf2QPXn2fpCDRliPd1HErJ1v4HkaqcGxdwyL6dYndnaUwhpzVBJI349lzcaNvByqttgdV/gTqkigELfP+iedxqAXyfSPDaJ3TVWW3ZAyvDojKM10Y0InAh19UyeEBveUQJOMYeUxHX4FRszWCOmhWk9tuxK4G6KuzAKj0iik9I3xwU4bYT4RnYJS5bhyJqZBXrco083Gh6i4O9Sa+eOx+z/rJJBFFwjHOKZo84PgaVQPgI/wDeb/+kp4TZrwwevcgKNSf51z5+q+QJzOjFCl4GDGxSpS8CMbfWiinHTMzhgKfjwQMOF2j41bE9BAPNA3RvYmWnPQGu3hvEuURvicixeBs4XiFrM/adUwYNs55eKz4NWqq0gPAl3VvcofYtdIC81dgvQXzXaTuJ6Wg+naNyy9J2ctjLpvF9aGLx3ZHob4sazUT5ozKyVkByayDaGNs2ZHkq7irVKIKQHOGvX7T2MlQnRdz8T9yuhRuBfLWWByIKSvTcs96HSl/lwyONiP9IMzlN9GgMPSdI8SYdxiLzrWrJpNYWFNBEG+4Zj8BJgXUVfyr8U9FOe06ohbHFANg3Y0Ez8ur3ntF5D26fLde+AKDfkXpQhEo/UdbPft1WCJTr3qcflAiPH7czz0/ljRJIwYmw+Nsk9i7VGVRKek4q84fPqkW36nIsNGYEwNsDSzkHVqyUiLev4I/mpnRaar7/PAJndCA5TJTkMcX1qfTqrWl5KrYU13fi60rfaMUCJGEPTHP0R9w1XNymaXOE0LjjfN//QvYGowQiiLqE3LOVxR3qd0Y8HX1vf4FyR6hyevVMQXom4p1JaAweTntpeo9puEsdsf+9oqvUvMFmOqPssYiTxhN6oTeCkvkP5b9/h+z6nmYeatHtlabat+oo+wROKvFU2h6tbOiivwP6snzYSWptk71fnGuZGQNmPcsPag8+HN4YrvmIakT51254uVa5dPL/w1F5mIF1FYB4l52K2/zUcVFcGsCShMWKxC5aNy6QbPzaOQhHpsQZO9TZ1nPD7VslFTl/68ue1wIxOi3YVK01r4dIfef10JYQYqsyAW+mWIqcsAWSwtEP/0wya0Se7zlyE9RNVnGGQ6WXJXM3nrujhe63VLD9vJOSM48fh1TaadvV9SmQfIP/10OS/R9Ia4tUTS8ifYytBhRyHfurFJBh+fAb9FA4keBZpZ4aRPwRoCQ3HB6/0dv5xtaid11W8/5nsWwd1aWtJooG/ckxudjCbVSlxhv6cCFqlkA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SE1P216MB1303.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(52116014)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lfL33ojQNp0oXDuDJTclyPCaV7jsfQ9GKm8FYzGOqCO6Jm6a6jmC5WAdsyQyjU5DaOta39Bs7LdvJqd+zL67w1JwtFcn4injf4gpBQE3C/X5h/qj9qgKrNIZYQlmSE8Yd4yFNnXFR9Zj3gvWJJIPTBVBF6c1jb5ipkMGGMc2RR6dWNje5NFE6QzlZRw8U5GSO2A5ZWTczVHif6XfU5kPx7SCyjyKqVlWT0L0AMjjb+W0D2AER9tttK0+QeVM7iejUAiVd3LL2XFYms0VjyaTswpwgpnELi8tjNXlTwa8Ejzc8VXwGn/I2Yr3KVwDqPfY2NVmvQiwno3Ur5mv7sydakLeqXewnO6JEbB/KsNko7DBuaZqHe0IvsP9Og018xVGftaLxkb1dA9AuoJPAOWBNLKw6PLvCw0f+V6Sy8arYncOnCB6aA+kFbgawBZXVaXU758ZfPR2PmNladTv1OkQpgJRipj+Bjf0Qlz56w8KLxDhv2I1Sg6907qSIPRPWjEA8ObolTxpjz58oa4NTTfqItzGAo/SpsASc2cXVprdxo7uhxz1n51whhn9k2ofAgiS+l1fUUNaMkfhDBm1XoFjaIoVCBpbli7pguwPXr2Pqab30pzqrs5Bstee6lPml+8DuZvOrydoir2yw4fSRCG3Mf4cARK6HK90s5Pnap8O5wc3VJ6IMvqnU4esw6+Wi3hmL4q+hri86ulSzuh0ChqHUhfj5mN6O7wVt/5pOXRQMgvR1seaTZBqwSFyk/AwzWft3/DiIVhmH0XT5QvUiW4lwFYNpiyD9+JC9Xy49fazSzkFNMZvv9Jk9FG1FibvCMjYV5yTieGKVPB0upLjCPWiqjH2d3masQZ7eRKXw8sYqYFL8YTnMAwPYl0Ij0lNo24NPOi0LC/8du8QCOK7+qd8rEohN2E5rpH+vdjW56Nkf89yyfSnJ+Om9+VrlaH9KAGLOnwP5aVI6RBDbVDz0p3qh3ojKyHTzibGKWRmkrpRpFbviFNWK36Ipq24eS6VxCvHp0t1+s1Hi00eiZaOuEW8vPNunIurPYM0UCD907hj1II8uAwZAEO8X5NlRTcdS1ElVAH0nq6TZob/dpaVEyDsFWhdHwSKStPxm2D/vcQahCts4GPcJjswC/n4W/1QCmhl7Gam0BbneYH0g9w6H42El/eGExKOHjiHiOzfrCNRmTKiQHwjkyK2UmNu8aDr69pPB1XGnye1w+hPzDcAWzm/d8bNr2XqrYoecrCZnQY9u+qM3miov4upa803ELOXg8PpQqhUJO+9QC0UHlrAiR/Yk2ETAdjck3FyShnge5ObCNXbwX4Fxpslv2GzcD4ssVCfcvy1esqT5OMZcfP1Umi67KhD8ZvgYcBCCIsBzc54dZGAQCTn7tmX/qi81ohoVuqQlnuHC9XAvyr0GQBIJMmQVjPLs4iOCy3jmRR8guYLuXHjTE53pManm/ERF7C3Zhw330HvTlDNJG5G+kHbiZblTYBzcLKy3O2yYwxt1UAjT2vTbIYXstWeKWUoGUyrBVr93l3uwER5tfJt1S/Yo3GCWmgHRZG4nRpthKyBlUjLqOZ+KDW5/zy9Uh6R5cTiizkT3jif8OUb1y+TvFo8uH+tVA== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ce200ae-d417-495e-7e1b-08dcba9d9783 X-MS-Exchange-CrossTenant-AuthSource: SE1P216MB1303.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 07:08:39.5900 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 63aQOa5fALN8xHhZWRyVZnE0fbzx0OUthzYNSaulpjDfjdQxC5v0nhPkwv8zZT5EraM/ZaywkyJDAHd5EMv5khULsBvYiNnrSr3ZU61gAss= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB1530 X-LSpam-Score: -6.3 (------) X-LSpam-Report: No, score=-6.3 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DMARC_MISSING=0.001,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_VALIDITY_CERTIFIED=-3,RCVD_IN_VALIDITY_RPBL=1.31,RCVD_IN_VALIDITY_SAFE=-2,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no Add support for runtime suspend/resume in the encoder and decoder. This is achieved by saving the VPU state and powering it off while the VPU idle. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-helper.c | 13 ----- .../platform/chips-media/wave5/wave5-hw.c | 4 +- .../chips-media/wave5/wave5-vpu-dec.c | 21 ++++++-- .../chips-media/wave5/wave5-vpu-enc.c | 20 ++++++-- .../platform/chips-media/wave5/wave5-vpu.c | 50 +++++++++++++++++++ .../platform/chips-media/wave5/wave5-vpuapi.c | 33 ++++++++++-- .../media/platform/chips-media/wave5/wave5.h | 3 ++ 7 files changed, 118 insertions(+), 26 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c index d60841c54a80..a20d84dbe3aa 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -58,7 +58,6 @@ int wave5_vpu_release_device(struct file *filp, char *name) { struct vpu_instance *inst = wave5_to_vpu_inst(filp->private_data); - struct vpu_device *dev = inst->dev; int ret = 0; v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx); @@ -78,18 +77,6 @@ int wave5_vpu_release_device(struct file *filp, } wave5_cleanup_instance(inst); - if (dev->irq < 0) { - ret = mutex_lock_interruptible(&dev->dev_lock); - if (ret) - return ret; - - if (list_empty(&dev->instances)) { - dev_dbg(dev->dev, "Disabling the hrtimer\n"); - hrtimer_cancel(&dev->hrtimer); - } - - mutex_unlock(&dev->dev_lock); - } return ret; } diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index 2a98bab446d0..c8a905994109 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -1228,8 +1228,8 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) return setup_wave5_properties(dev); } -static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, - size_t size) +int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, + size_t size) { u32 reg_val; struct vpu_buf *common_vb; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 0c5c9a8de91f..698c83e3082e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -5,6 +5,7 @@ * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ +#include #include "wave5-helper.h" #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" @@ -518,6 +519,8 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst) if (q_status.report_queue_count == 0 && (q_status.instance_queue_count == 0 || dec_info.sequence_changed)) { dev_dbg(inst->dev->dev, "%s: finishing job.\n", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } } @@ -1398,6 +1401,7 @@ static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count int ret = 0; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); v4l2_m2m_update_start_streaming_state(m2m_ctx, q); @@ -1429,13 +1433,15 @@ static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count if (ret) goto return_buffers; } - + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; free_bitstream_vbuf: wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); return_buffers: wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; } @@ -1521,6 +1527,7 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) bool check_cmd = TRUE; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); while (check_cmd) { struct queue_status_info q_status; @@ -1544,6 +1551,9 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) streamoff_output(q); else streamoff_capture(q); + + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); } static const struct vb2_ops wave5_vpu_dec_vb2_ops = { @@ -1630,7 +1640,7 @@ static void wave5_vpu_dec_device_run(void *priv) int ret = 0; dev_dbg(inst->dev->dev, "%s: Fill the ring buffer with new bitstream data", __func__); - + pm_runtime_resume_and_get(inst->dev->dev); ret = fill_ringbuffer(inst); if (ret) { dev_warn(inst->dev->dev, "Filling ring buffer failed\n"); @@ -1713,6 +1723,8 @@ static void wave5_vpu_dec_device_run(void *priv) finish_job_and_return: dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } @@ -1879,9 +1891,8 @@ static int wave5_vpu_open_dec(struct file *filp) if (ret) goto cleanup_inst; - if (dev->irq < 0 && !hrtimer_active(&dev->hrtimer) && list_empty(&dev->instances)) - hrtimer_start(&dev->hrtimer, ns_to_ktime(dev->vpu_poll_interval * NSEC_PER_MSEC), - HRTIMER_MODE_REL_PINNED); + if (list_empty(&dev->instances)) + pm_runtime_use_autosuspend(inst->dev->dev); list_add_tail(&inst->list, &dev->instances); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index b731decbfda6..985de0c293e2 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -5,6 +5,7 @@ * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ +#include #include "wave5-helper.h" #define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" @@ -1310,6 +1311,7 @@ static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret = 0; + pm_runtime_resume_and_get(inst->dev->dev); v4l2_m2m_update_start_streaming_state(m2m_ctx, q); if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { @@ -1364,9 +1366,13 @@ static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count if (ret) goto return_buffers; + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return 0; return_buffers: wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; } @@ -1408,6 +1414,7 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) */ dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); if (wave5_vpu_both_queues_are_streaming(inst)) switch_state(inst, VPU_INST_STATE_STOP); @@ -1432,6 +1439,9 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) streamoff_output(inst, q); else streamoff_capture(inst, q); + + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); } static const struct vb2_ops wave5_vpu_enc_vb2_ops = { @@ -1478,6 +1488,7 @@ static void wave5_vpu_enc_device_run(void *priv) u32 fail_res = 0; int ret = 0; + pm_runtime_resume_and_get(inst->dev->dev); switch (inst->state) { case VPU_INST_STATE_PIC_RUN: ret = start_encode(inst, &fail_res); @@ -1491,6 +1502,8 @@ static void wave5_vpu_enc_device_run(void *priv) break; } dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return; default: WARN(1, "Execution of a job in state %s is invalid.\n", @@ -1498,6 +1511,8 @@ static void wave5_vpu_enc_device_run(void *priv) break; } dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } @@ -1739,9 +1754,8 @@ static int wave5_vpu_open_enc(struct file *filp) if (ret) goto cleanup_inst; - if (dev->irq < 0 && !hrtimer_active(&dev->hrtimer) && list_empty(&dev->instances)) - hrtimer_start(&dev->hrtimer, ns_to_ktime(dev->vpu_poll_interval * NSEC_PER_MSEC), - HRTIMER_MODE_REL_PINNED); + if (list_empty(&dev->instances)) + pm_runtime_use_autosuspend(inst->dev->dev); list_add_tail(&inst->list, &dev->instances); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 7273254ecb03..41c4bf64f27d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "wave5-vpu.h" #include "wave5-regdefine.h" @@ -153,6 +154,45 @@ static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, return 0; } +static __maybe_unused int wave5_pm_suspend(struct device *dev) +{ + struct vpu_device *vpu = dev_get_drvdata(dev); + + if (pm_runtime_suspended(dev)) + return 0; + + if (vpu->irq < 0) + hrtimer_cancel(&vpu->hrtimer); + + wave5_vpu_sleep_wake(dev, true, NULL, 0); + clk_bulk_disable_unprepare(vpu->num_clks, vpu->clks); + + return 0; +} + +static __maybe_unused int wave5_pm_resume(struct device *dev) +{ + struct vpu_device *vpu = dev_get_drvdata(dev); + int ret = 0; + + wave5_vpu_sleep_wake(dev, false, NULL, 0); + ret = clk_bulk_prepare_enable(vpu->num_clks, vpu->clks); + if (ret) { + dev_err(dev, "Enabling clocks, fail: %d\n", ret); + return ret; + } + + if (vpu->irq < 0 && !hrtimer_active(&vpu->hrtimer)) + hrtimer_start(&vpu->hrtimer, ns_to_ktime(vpu->vpu_poll_interval * NSEC_PER_MSEC), + HRTIMER_MODE_REL_PINNED); + + return ret; +} + +static const struct dev_pm_ops wave5_pm_ops = { + SET_RUNTIME_PM_OPS(wave5_pm_suspend, wave5_pm_resume, NULL) +}; + static int wave5_vpu_probe(struct platform_device *pdev) { int ret; @@ -281,6 +321,12 @@ static int wave5_vpu_probe(struct platform_device *pdev) (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : ""); dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision); + + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + wave5_vpu_sleep_wake(&pdev->dev, true, NULL, 0); + return 0; err_enc_unreg: @@ -310,6 +356,9 @@ static void wave5_vpu_remove(struct platform_device *pdev) hrtimer_cancel(&dev->hrtimer); } + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + mutex_destroy(&dev->dev_lock); mutex_destroy(&dev->hw_lock); reset_control_assert(dev->resets); @@ -337,6 +386,7 @@ static struct platform_driver wave5_vpu_driver = { .driver = { .name = VPU_PLATFORM_DEVICE_NAME, .of_match_table = of_match_ptr(wave5_dt_ids), + .pm = &wave5_pm_ops, }, .probe = wave5_vpu_probe, .remove_new = wave5_vpu_remove, diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c index 1a3efb638dde..e16b990041c2 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include "wave5-vpuapi.h" #include "wave5-regdefine.h" #include "wave5.h" @@ -195,14 +197,20 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) int retry = 0; struct vpu_device *vpu_dev = inst->dev; int i; + int inst_count = 0; + struct vpu_instance *inst_elm; *fail_res = 0; if (!inst->codec_info) return -EINVAL; + pm_runtime_resume_and_get(inst->dev->dev); + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); - if (ret) + if (ret) { + pm_runtime_put_sync(inst->dev->dev); return ret; + } do { ret = wave5_vpu_dec_finish_seq(inst, fail_res); @@ -232,9 +240,14 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); + list_for_each_entry(inst_elm, &vpu_dev->instances, list) + inst_count++; + if (inst_count == 1) + pm_runtime_dont_use_autosuspend(vpu_dev->dev); + unlock_and_return: mutex_unlock(&vpu_dev->hw_lock); - + pm_runtime_put_sync(inst->dev->dev); return ret; } @@ -697,25 +710,33 @@ int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) int ret; int retry = 0; struct vpu_device *vpu_dev = inst->dev; + int inst_count = 0; + struct vpu_instance *inst_elm; *fail_res = 0; if (!inst->codec_info) return -EINVAL; + pm_runtime_resume_and_get(inst->dev->dev); + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); - if (ret) + if (ret) { + pm_runtime_resume_and_get(inst->dev->dev); return ret; + } do { ret = wave5_vpu_enc_finish_seq(inst, fail_res); if (ret < 0 && *fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) { dev_warn(inst->dev->dev, "enc_finish_seq timed out\n"); + pm_runtime_resume_and_get(inst->dev->dev); mutex_unlock(&vpu_dev->hw_lock); return ret; } if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING && retry++ >= MAX_FIRMWARE_CALL_RETRY) { + pm_runtime_resume_and_get(inst->dev->dev); mutex_unlock(&vpu_dev->hw_lock); return -ETIMEDOUT; } @@ -734,7 +755,13 @@ int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_task); + list_for_each_entry(inst_elm, &vpu_dev->instances, list) + inst_count++; + if (inst_count == 1) + pm_runtime_dont_use_autosuspend(vpu_dev->dev); + mutex_unlock(&vpu_dev->hw_lock); + pm_runtime_put_sync(inst->dev->dev); return 0; } diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h index 2a29b9164f97..2caab356f3e1 100644 --- a/drivers/media/platform/chips-media/wave5/wave5.h +++ b/drivers/media/platform/chips-media/wave5/wave5.h @@ -62,6 +62,9 @@ int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision); int wave5_vpu_init(struct device *dev, u8 *fw, size_t size); +int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, + size_t size); + int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode); int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param); From patchwork Mon Aug 12 07:08:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "jackson.lee" X-Patchwork-Id: 103408 X-Patchwork-Delegate: sebastian.fricke@collabora.com Received: from am.mirrors.kernel.org ([147.75.80.249]) by linuxtv.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sdPBd-0004dP-2C for patchwork@linuxtv.org; Mon, 12 Aug 2024 07:09:51 +0000 Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 6F4C51F22B4A for ; Mon, 12 Aug 2024 07:09:47 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1B093168497; Mon, 12 Aug 2024 07:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="extC0sd9" X-Original-To: linux-media@vger.kernel.org Received: from SLXP216CU001.outbound.protection.outlook.com (mail-koreacentralazon11021080.outbound.protection.outlook.com [40.107.42.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E25166F3C; Mon, 12 Aug 2024 07:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.42.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446534; cv=fail; b=Qm5Y8V7W8MIUCeJuHufP/+h1/Lfa52ptjtoVMtGg7l7RJMnPqVHGgdWT3xjYBXd0xDBqyWTzlpufQkQsNPIIqCTUEFdxPaqNPPV8jVuixW59cCcJ+0Pf6uLhPmSGim8SzoAirOxUmS0wXBZ46Jc4/LTzkfzMsOcbxAqSV9CtvP4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446534; c=relaxed/simple; bh=zW4I4v0NQdcUDXHy+lmoXAacaRZPzRBb0G0/0bUC/KA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=EritLsp9LdLCuRHicAgy9DRG0akGLrTCNePam+SsfTxlIIqanWttVe2MjAzeiaofhSnhqCVbIyLhsshTeSDADpynN7ItGrl6t93VdamT6OonTwPSTT5ebfmXZOogqEdGIEC25uZv/X7OpKBGT7GWJ2RmZbO1kaVOlGyu7uko72I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=extC0sd9; arc=fail smtp.client-ip=40.107.42.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Z2q+vgI6w1A0h2Z81Ovcupn5L4KfB43ZlBZjFRTW40OJWbDNNiwntcBrPiMIsta+H5bSwQpaX3JAdUYeqpH8lmfx7kthX26sXiZs16aJQj2Bw6Ja8NXB0TO7v0dx7h249UnSUpV9VxcnawYciMN2D1z+Fu/xP74CJFEGCvDqClMC4zi1IsUocCydY2fvhAKNDOHLNpsrF73FpOHuSVVheWE3iPfN0arFtf5Tc0vS9M4xrOiEiCyoeY8c94JknGNAf/r0ATfVHflpZpHJk41zQ8i1jB8CSZjCPWmqqVEi1EXsiAzr9ihJxIYM8v/9XXOhun/gJLCtFOr4CpSK5cyjgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X5cOAfF5yTQ79VK7mV35avobbefMkQD7z3V0M7nW+Ew=; b=PzlYXP6grIUlWqMGucM42MQ8dBa6mkXkd80C1X+iymdQjn/rAaqXzW3Fuz23uDwEOWIt2LGz0HyvFNX0b7HXM+HDNjahGO11ceWk69c3c8hQW1DBk6S6iIoL+03pvr76xpegFpnBMvrZ2KDS/Gp1/PSsLNztn1Eb4s7gHgWPLo34759PQO8P6Y5N4DUsy9sBIeK5zaW5gMIH5VXG2i4PtN79ooJXeCFrjnPsU/2ZNGVIBQ7irSDf/B4wTfFexRVyF0UmbDNJoPVLukitugD+8BsP5Rt8pjeX8jZO8oCc7NejtAQpIp5UvYXcLcsjqB44kd81slI7BiP3CD6KBsSrNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X5cOAfF5yTQ79VK7mV35avobbefMkQD7z3V0M7nW+Ew=; b=extC0sd9KKqIIVT6z9bFTPkGBri3p+SMatRT+cvwUIfDNwjjpPjekeb87+yRNbjS+nReaEg1m9TXgFgg5wFmShNJN0cZ9j+EPnIZ3a3f8WXNiDAaeq2wGfdDZgGrIkXzH0K58T/tf3Wct01OxgmkwCihFQXXIbSzrtZOneausho= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) by SL2P216MB1530.KORP216.PROD.OUTLOOK.COM (2603:1096:101:33::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 07:08:40 +0000 Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b]) by SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b%7]) with mapi id 15.20.7849.019; Mon, 12 Aug 2024 07:08:40 +0000 From: "Jackson.lee" To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipsnmedia.com, Nicolas Dufresne Subject: [RESEND PATCH v7 3/4] media: chips-media: wave5: Use helpers to calculate bytesperline and sizeimage. Date: Mon, 12 Aug 2024 16:08:22 +0900 Message-Id: <20240812070823.125-4-jackson.lee@chipsnmedia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812070823.125-1-jackson.lee@chipsnmedia.com> References: <20240812070823.125-1-jackson.lee@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0154.KORP216.PROD.OUTLOOK.COM (2603:1096:101:35::18) To SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SE1P216MB1303:EE_|SL2P216MB1530:EE_ X-MS-Office365-Filtering-Correlation-Id: e528adea-b9af-45f9-001d-08dcba9d9804 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: eFp0fMqdo3xD1OkWDTXF0bs5gJVJ4kMmAzGjagmNcw+TbQGVM/T5MxyNHEPOEFzFq03oopECbIsckrerdvJemPulkULAu4lU7tMpwkH5VU+/cpsnMxnEQbkQWM9srWj74JuXGtk+n4FAYBXx/lKmZhqKazBYaw3g36bHjYp/ScT7H5IxSL+GHd6b0IBHPwLU1v6hH2d2fHpJlmsb+UZAXjkG8MN3WMKEDeKzrFMNzrC5Md8G2dpQL5Gp2e6hFOV6ks0Lfy1/KEkWwXx8DBHwxf7bm0D2JqI2gOw5h8AaWuJa1mSTgxRy6zo9ZFGevWcnEAwbMpmvpGHiAtXPawRNz2b5cKph0SZrn+pMPR/BLWXYqwA8Qvr4QFfeNAWrqRftCX2Llo+QqZYScIA5/EzSRQesNnlFxteEJr2xrWDAnNtoXHPb+wmoX3FdK3GjRkI80Dw3R54clzZXwsuTsGUJSC2ogMgz310M9Xh9Y8mLzDusXl1hXPheZb4aTWmNTjWrVleLHzSQ/r+czleSrSXP7FrCi0ECk5nCg8QfRV7U6HKEkB0wgUUSocKtS/rLYfYuVoBRrk+d+DzFFSDS6NmqRmD7WGBb/vITTOY+/jBGu4hSZKf4NaPBwF8NUxryejBIeP3rTnEDD/zO/PJ5XIpqywRndUQ+w0586B8qS1JEuE7m5hurAPkdspkfOoUrA+NX3Rno+zmzY/b4r/uzU7XIUFFchpwd2a6xY5Cd1k01GLcaktsYxjnuaBMH893zQktJ4yMed1vOvFnmMJ8sjfE2TjCr4MIpU/HQLoEuBdnKkTazusXumeaqcCpWJMnGJA/Srh08BmciZV6dmj4RvGS5WLGz4x1Sc03vxfVSVF8pckhg6f2f0C3Redm7aobGY4bmP3CBQusisJdOLcD97VnUI7AbDYijs6cIfDHioi3MzFVbR5UkQyVDIHO7sNcTyDj4cvoD8PKHpX5f5gUNBy43Pscp8B4avDi7mRq+qmq7CoCLLA6SRrp14C4s9uA6v25GV+9Bg3NH/6s866+zZbxbG7DKcEQjU7LEbyDt31h4oixpwWAxx++2DuOHNDY0nzQoHrTOXbJOWqWmphMRSBpv7LYEVLZqp9Xr+qX1pyBICb+UgRLP7njR58cNllfr8mDDXjB0BBTCeqIaMyFXpsATRi783emZmKEdnSt5heJIwtXfvXqfChX6gS890anTV4KhvK1gCAVsLSyDx4mAmDvFsFdKq5k52fvdXfZUKx8FxBM5JS+EwmZJvz5vT4I1PN3ViAyK8kfv8Aes3mF6Emirpr4HjnRBGtelZ6vOJWXWZw0ZZIL+cHvyBOBolxSfTYufnEUV6YXbJFBF9MgOeqDppVVE8jCdwNiY4ou6Eag1ZLYK8LWg1bt6DG/Rz9FiiHr9L/25k9lCQSGCfvwiriHieg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SE1P216MB1303.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(52116014)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FjZ4nB/OQTI7q3dfNE2Y4JQPYwqGirRnQDmAQKGT5KDilL7YOwI0AFmquFgawhK3nh+nMjN7OacDIfKGk/3oUzWiW2dycc31vtWYFoNLMLqCJcbW8W4NnK92/fXDj0Vio4PHF3lcwQHVPwCth1ecSEGp0BwGa+AoiucZ4CprYMmN7RhglsxJjg+rIVk2NQAvXhVcgnxM1efFjBgA5Fm1u9pqhKSuB61SMg1OrVpp3fFgSdSrGkRX4zAGExUcUuy2bjaQqmKd97OaHNRCwWoxHvNrIc1n7kkND/ZkDFQhEjp35gg7Ob+TmHtZjOYgCy+wih+a0Xeq2Vhi6UUq72UPCRCzQEOW6oh+Q9+LNyO9+dcWwwCi6OrD5/4j7UyPkcRADlBHW7rAMjPurLvB0ekOsJ5VSHa36Y3rboyRdssUrbJ1VNle9PGcnJ7OlhyL/q4bAtFqodj1Hqo4gWfqtace77JMhw7uT+No+FKBM2JsuHG/WKD8BMj9aoryz9rGv0LnAFj/84aPwfIAxmP6nWDoSfLs5IbXYAIqZPLAk4VYPW7xWOUBnbwE30BiDXju20qZ2j9+dSnXDAzlgPOynXtfpENiajGgo4smDx4BxgIcdIl6Ng+2aRBy74qvBljune4dt+4hgRPN5HZKbKI0ej4gASm+AdJ4YjcLSw4WKLd7puCEdMuJS/b08VcFT/7L2K82esVAb/K/QjZyHSWwhEPNJjO17LehfGzBUarzN0InnhlRaqJj61Uq3Zd2QrwnF9/vPi7RWpvDAItGEZeC/17bHU5BYkqa14wMdkdrP+nlqX3iU4Ewz2qYV87PSJPVYKUtU4NbTmKQz9NQsn5BgAflpCcJBlrogMGsrOX1mRDkRp6DWXSyuyykrto99XmAiICqJD6p7kiWwgNuBBG7eG1doSDzVi/ys3lacWDDZ7YENEpwTWjEsac9crom78ah587/ihBP6dUv2QGCuQ7wxrZFIB2oHRLfHmB6no6TcZq10nHsJs0GBlqTnFT4iydJ7nyutB0fefEvvS85PbOeU91EaGai1Wx77OfH7sIFO5C1ZF+AEMwphRtOY0X77Q2MNqGLUKPjcJBioW5hcmt7ariElq23hh+FrRjo5MeGsWIPPjubk3WYcNV3aUD9YEo3IHY4YSew4yCE2TJ3yhbsWSqOl+SlY89JkdfvTLkeWagL+tgmmstAxIlCcDGCTKOiJCfKb4Ln70h1Ahef69RbBKDOZJ96x19wn3SGQg7asczqp9Auv7jplq6vZbvO0A/TYQE4+PDXQaDEkneLS2IN8USmFvY+y9PmJlfS9LdRLBj1rSHiAKEbAZg9YtVphMBKA0gJqrtkBiWmlgaR1JQ9FdR1MzfBC0+qhwdvCXszbggSwBLjl/0FGR6B6G7OGgaDubqqJvZtOiOP22g4O/YRBF+PcS7M0jwS5EwruqOjmKk/5FsYif698DO6SFOwlLCbAJDgThP0DmhswQMkaQZZs8tyFbvQzzcTwW9YnVOjaC7cCXKqSpFX8kr2zkIgaWCQf59SHLrulZawhxs7TsbrsjKqj5gcXHiNOVvY6scEVmLYOlPjQqtxGtf+HJ2IYgrkjh/vddbwp7qg9cNGyLD79T2Cbw== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e528adea-b9af-45f9-001d-08dcba9d9804 X-MS-Exchange-CrossTenant-AuthSource: SE1P216MB1303.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 07:08:40.4049 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AqdgUm41v/7CxONXsXJ/rsNNrVtftmq72ghZoEPoGu6DJkcVspBOiW4X5NwsA5ARpPlcsPn+Y6D7Z5IldhfGIGwt5YTW6m5nilUrhWO7VTQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB1530 X-LSpam-Score: -6.3 (------) X-LSpam-Report: No, score=-6.3 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DMARC_MISSING=0.001,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_VALIDITY_CERTIFIED=-3,RCVD_IN_VALIDITY_RPBL=1.31,RCVD_IN_VALIDITY_SAFE=-2,SPF_HELO_NONE=0.001,SPF_PASS=-0.001,T_PDS_OTHER_BAD_TLD=0.01 autolearn=ham autolearn_force=no Use v4l2-common helper functions to calculate bytesperline and sizeimage, instead of calculating in a wave5 driver directly. In case of raw(YUV) v4l2_pix_format, the wave5 driver updates v4l2_pix_format_mplane struct through v4l2_fill_pixfmt_mp() function. Encoder and Decoder need same bytesperline and sizeimage values for same v4l2_pix_format. So, a wave5_update_pix_fmt is refactored to support both together. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-helper.c | 24 ++ .../platform/chips-media/wave5/wave5-helper.h | 5 + .../chips-media/wave5/wave5-vpu-dec.c | 300 +++++++----------- .../chips-media/wave5/wave5-vpu-enc.c | 197 +++++------- .../platform/chips-media/wave5/wave5-vpu.h | 5 +- .../chips-media/wave5/wave5-vpuconfig.h | 27 +- 6 files changed, 239 insertions(+), 319 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c index a20d84dbe3aa..2c9d8cbca6e4 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -7,6 +7,8 @@ #include "wave5-helper.h" +#define DEFAULT_BS_SIZE(width, height) ((width) * (height) / 8 * 3) + const char *state_to_str(enum vpu_instance_state state) { switch (state) { @@ -217,3 +219,25 @@ void wave5_return_bufs(struct vb2_queue *q, u32 state) v4l2_m2m_buf_done(vbuf, state); } } + +void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, + int pix_fmt_type, + unsigned int width, + unsigned int height, + const struct v4l2_frmsize_stepwise *frmsize) +{ + v4l2_apply_frmsize_constraints(&width, &height, frmsize); + + if (pix_fmt_type == VPU_FMT_TYPE_CODEC) { + pix_mp->width = width; + pix_mp->height = height; + pix_mp->num_planes = 1; + pix_mp->plane_fmt[0].bytesperline = 0; + pix_mp->plane_fmt[0].sizeimage = max(DEFAULT_BS_SIZE(width, height), + pix_mp->plane_fmt[0].sizeimage); + } else { + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, width, height); + } + pix_mp->flags = 0; + pix_mp->field = V4L2_FIELD_NONE; +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h index 6cee1c14d3ce..9937fce553fc 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.h +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h @@ -28,4 +28,9 @@ const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, const struct vpu_format fmt_list[MAX_FMTS]); enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type); void wave5_return_bufs(struct vb2_queue *q, u32 state); +void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, + int pix_fmt_type, + unsigned int width, + unsigned int height, + const struct v4l2_frmsize_stepwise *frmsize); #endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 698c83e3082e..99e929aab870 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -11,111 +11,92 @@ #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" #define VPU_DEC_DRV_NAME "wave5-dec" -#define DEFAULT_SRC_SIZE(width, height) ({ \ - (width) * (height) / 8 * 3; \ -}) +static const struct v4l2_frmsize_stepwise dec_hevc_frmsize = { + .min_width = W5_MIN_DEC_PIC_8_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_8_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_CODEC_STEP_HEIGHT, +}; + +static const struct v4l2_frmsize_stepwise dec_h264_frmsize = { + .min_width = W5_MIN_DEC_PIC_32_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_32_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_CODEC_STEP_HEIGHT, +}; + +static const struct v4l2_frmsize_stepwise dec_raw_frmsize = { + .min_width = W5_MIN_DEC_PIC_8_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_RAW_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_8_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_RAW_STEP_HEIGHT, +}; static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { [VPU_FMT_TYPE_CODEC] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_hevc_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_H264, - .max_width = 8192, - .min_width = 32, - .max_height = 4320, - .min_height = 32, + .v4l2_frmsize = &dec_h264_frmsize, }, }, [VPU_FMT_TYPE_RAW] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV16, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV61, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV16M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV61M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_raw_frmsize, }, } }; @@ -234,74 +215,6 @@ static void wave5_handle_src_buffer(struct vpu_instance *inst, dma_addr_t rd_ptr inst->remaining_consumed_bytes = consumed_bytes; } -static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, - unsigned int height) -{ - switch (pix_mp->pixelformat) { - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_NV21: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2; - break; - case V4L2_PIX_FMT_YUV422P: - case V4L2_PIX_FMT_NV16: - case V4L2_PIX_FMT_NV61: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height * 2; - break; - case V4L2_PIX_FMT_YUV420M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = width * height / 4; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = width * height / 4; - break; - case V4L2_PIX_FMT_NV12M: - case V4L2_PIX_FMT_NV21M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = width * height / 2; - break; - case V4L2_PIX_FMT_YUV422M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = width * height / 2; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = width * height / 2; - break; - case V4L2_PIX_FMT_NV16M: - case V4L2_PIX_FMT_NV61M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = width * height; - break; - default: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = 0; - pix_mp->plane_fmt[0].sizeimage = max(DEFAULT_SRC_SIZE(width, height), - pix_mp->plane_fmt[0].sizeimage); - break; - } -} - static int start_decode(struct vpu_instance *inst, u32 *fail_res) { struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; @@ -389,6 +302,8 @@ static int handle_dynamic_resolution_change(struct vpu_instance *inst) } if (p_dec_info->initial_info_obtained) { + const struct vpu_format *vpu_fmt; + inst->conf_win.left = initial_info->pic_crop_rect.left; inst->conf_win.top = initial_info->pic_crop_rect.top; inst->conf_win.width = initial_info->pic_width - @@ -396,10 +311,27 @@ static int handle_dynamic_resolution_change(struct vpu_instance *inst) inst->conf_win.height = initial_info->pic_height - initial_info->pic_crop_rect.top - initial_info->pic_crop_rect.bottom; - wave5_update_pix_fmt(&inst->src_fmt, initial_info->pic_width, - initial_info->pic_height); - wave5_update_pix_fmt(&inst->dst_fmt, initial_info->pic_width, - initial_info->pic_height); + vpu_fmt = wave5_find_vpu_fmt(inst->src_fmt.pixelformat, + dec_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->src_fmt, + VPU_FMT_TYPE_CODEC, + initial_info->pic_width, + initial_info->pic_height, + vpu_fmt->v4l2_frmsize); + + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, + dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, + VPU_FMT_TYPE_RAW, + initial_info->pic_width, + initial_info->pic_height, + vpu_fmt->v4l2_frmsize); } v4l2_event_queue_fh(fh, &vpu_event_src_ch); @@ -548,12 +480,12 @@ static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_f } fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = vpu_fmt->min_width; - fsize->stepwise.max_width = vpu_fmt->max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = vpu_fmt->min_height; - fsize->stepwise.max_height = vpu_fmt->max_height; - fsize->stepwise.step_height = 1; + fsize->stepwise.min_width = vpu_fmt->v4l2_frmsize->min_width; + fsize->stepwise.max_width = vpu_fmt->v4l2_frmsize->max_width; + fsize->stepwise.step_width = W5_DEC_CODEC_STEP_WIDTH; + fsize->stepwise.min_height = vpu_fmt->v4l2_frmsize->min_height; + fsize->stepwise.max_height = vpu_fmt->v4l2_frmsize->max_height; + fsize->stepwise.step_height = W5_DEC_CODEC_STEP_HEIGHT; return 0; } @@ -576,6 +508,7 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo { struct vpu_instance *inst = wave5_to_vpu_inst(fh); struct dec_info *p_dec_info = &inst->codec_info->dec_info; + const struct v4l2_frmsize_stepwise *frmsize; const struct vpu_format *vpu_fmt; int width, height; @@ -589,14 +522,12 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo width = inst->dst_fmt.width; height = inst->dst_fmt.height; f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; + frmsize = &dec_raw_frmsize; } else { - const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); - - width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = info->mem_planes; + frmsize = vpu_fmt->v4l2_frmsize; } if (p_dec_info->initial_info_obtained) { @@ -604,9 +535,8 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo height = inst->dst_fmt.height; } - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_RAW, + width, height, frmsize); f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; f->fmt.pix_mp.quantization = inst->quantization; @@ -718,7 +648,9 @@ static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_f static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct v4l2_frmsize_stepwise *frmsize; const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", @@ -727,20 +659,19 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { + width = inst->src_fmt.width; + height = inst->src_fmt.height; f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); + frmsize = &dec_hevc_frmsize; } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = 1; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + frmsize = vpu_fmt->v4l2_frmsize; } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_CODEC, + width, height, frmsize); return 0; } @@ -748,6 +679,7 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; int i, ret; dev_dbg(inst->dev->dev, @@ -782,7 +714,13 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; - wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_RAW, + f->fmt.pix_mp.width, f->fmt.pix_mp.height, + vpu_fmt->v4l2_frmsize); return 0; } @@ -1005,6 +943,7 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff struct vpu_instance *inst = vb2_get_drv_priv(q); struct v4l2_pix_format_mplane inst_format = (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; + unsigned int i; dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, *num_buffers, *num_planes, q->type); @@ -1018,31 +957,9 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff if (*num_buffers < inst->fbc_buf_count) *num_buffers = inst->fbc_buf_count; - if (*num_planes == 1) { - if (inst->output_format == FORMAT_422) - sizes[0] = inst_format.width * inst_format.height * 2; - else - sizes[0] = inst_format.width * inst_format.height * 3 / 2; - dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); - } else if (*num_planes == 2) { - sizes[0] = inst_format.width * inst_format.height; - if (inst->output_format == FORMAT_422) - sizes[1] = inst_format.width * inst_format.height; - else - sizes[1] = inst_format.width * inst_format.height / 2; - dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", - __func__, sizes[0], sizes[1]); - } else if (*num_planes == 3) { - sizes[0] = inst_format.width * inst_format.height; - if (inst->output_format == FORMAT_422) { - sizes[1] = inst_format.width * inst_format.height / 2; - sizes[2] = inst_format.width * inst_format.height / 2; - } else { - sizes[1] = inst_format.width * inst_format.height / 4; - sizes[2] = inst_format.width * inst_format.height / 4; - } - dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", - __func__, sizes[0], sizes[1], sizes[2]); + for (i = 0; i < *num_planes; i++) { + sizes[i] = inst_format.plane_fmt[i].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); } } @@ -1568,20 +1485,15 @@ static const struct vb2_ops wave5_vpu_dec_vb2_ops = { static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, struct v4l2_pix_format_mplane *dst_fmt) { - unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; - const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); - src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; - src_fmt->field = V4L2_FIELD_NONE; - src_fmt->flags = 0; - src_fmt->num_planes = 1; - wave5_update_pix_fmt(src_fmt, 720, 480); - - dst_fmt->pixelformat = dst_pix_fmt; - dst_fmt->field = V4L2_FIELD_NONE; - dst_fmt->flags = 0; - dst_fmt->num_planes = dst_fmt_info->mem_planes; - wave5_update_pix_fmt(dst_fmt, 736, 480); + wave5_update_pix_fmt(src_fmt, VPU_FMT_TYPE_CODEC, + W5_DEF_DEC_PIC_WIDTH, W5_DEF_DEC_PIC_HEIGHT, + &dec_hevc_frmsize); + + dst_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + wave5_update_pix_fmt(dst_fmt, VPU_FMT_TYPE_RAW, + W5_DEF_DEC_PIC_WIDTH, W5_DEF_DEC_PIC_HEIGHT, + &dec_raw_frmsize); } static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 985de0c293e2..ef9aa1562346 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -11,65 +11,60 @@ #define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" #define VPU_ENC_DRV_NAME "wave5-enc" +static const struct v4l2_frmsize_stepwise enc_frmsize[FMT_TYPES] = { + [VPU_FMT_TYPE_CODEC] = { + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .step_width = W5_ENC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .step_height = W5_ENC_CODEC_STEP_HEIGHT, + }, + [VPU_FMT_TYPE_RAW] = { + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .step_width = W5_ENC_RAW_STEP_WIDTH, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .step_height = W5_ENC_RAW_STEP_HEIGHT, + }, +}; + static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { [VPU_FMT_TYPE_CODEC] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_H264, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], }, }, [VPU_FMT_TYPE_RAW] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, } }; @@ -106,46 +101,6 @@ static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state return -EINVAL; } -static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, - unsigned int height) -{ - switch (pix_mp->pixelformat) { - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_NV21: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; - break; - case V4L2_PIX_FMT_YUV420M: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; - break; - case V4L2_PIX_FMT_NV12M: - case V4L2_PIX_FMT_NV21M: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; - break; - default: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = 0; - pix_mp->plane_fmt[0].sizeimage = width * height / 8 * 3; - break; - } -} - static int start_encode(struct vpu_instance *inst, u32 *fail_res) { struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; @@ -360,13 +315,8 @@ static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_f return -EINVAL; } - fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = vpu_fmt->min_width; - fsize->stepwise.max_width = vpu_fmt->max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = vpu_fmt->min_height; - fsize->stepwise.max_height = vpu_fmt->max_height; - fsize->stepwise.step_height = 1; + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise = enc_frmsize[VPU_FMT_TYPE_CODEC]; return 0; } @@ -391,7 +341,9 @@ static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_f static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct v4l2_frmsize_stepwise *frmsize; const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, @@ -399,20 +351,19 @@ static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { + width = inst->dst_fmt.width; + height = inst->dst_fmt.height; f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); + frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC]; } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = 1; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + frmsize = vpu_fmt->v4l2_frmsize; } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_CODEC, + width, height, frmsize); f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; f->fmt.pix_mp.quantization = inst->quantization; @@ -499,7 +450,9 @@ static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_f static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct v4l2_frmsize_stepwise *frmsize; const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, @@ -507,28 +460,26 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); if (!vpu_fmt) { + width = inst->src_fmt.width; + height = inst->src_fmt.height; f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); + frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW]; } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = info->mem_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + frmsize = vpu_fmt->v4l2_frmsize; } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; - + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_RAW, + width, height, frmsize); return 0; } static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; int i, ret; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", @@ -568,7 +519,15 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; - wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_CODEC, + f->fmt.pix_mp.width, f->fmt.pix_mp.height, + vpu_fmt->v4l2_frmsize); + inst->conf_win.width = inst->dst_fmt.width; + inst->conf_win.height = inst->dst_fmt.height; return 0; } @@ -584,12 +543,17 @@ static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_se switch (s->target) { case V4L2_SEL_TGT_CROP_DEFAULT: case V4L2_SEL_TGT_CROP_BOUNDS: - case V4L2_SEL_TGT_CROP: s->r.left = 0; s->r.top = 0; s->r.width = inst->dst_fmt.width; s->r.height = inst->dst_fmt.height; break; + case V4L2_SEL_TGT_CROP: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->conf_win.width; + s->r.height = inst->conf_win.height; + break; default: return -EINVAL; } @@ -612,8 +576,10 @@ static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_se s->r.left = 0; s->r.top = 0; - s->r.width = inst->src_fmt.width; - s->r.height = inst->src_fmt.height; + s->r.width = min(s->r.width, inst->dst_fmt.width); + s->r.height = min(s->r.height, inst->dst_fmt.height); + + inst->conf_win = s->r; return 0; } @@ -1151,8 +1117,8 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, open_param->wave_param.lambda_scaling_enable = 1; open_param->line_buf_int_en = true; - open_param->pic_width = inst->dst_fmt.width; - open_param->pic_height = inst->dst_fmt.height; + open_param->pic_width = inst->conf_win.width; + open_param->pic_height = inst->conf_win.height; open_param->frame_rate_info = inst->frame_rate; open_param->rc_enable = inst->rc_enable; if (inst->rc_enable) { @@ -1456,20 +1422,15 @@ static const struct vb2_ops wave5_vpu_enc_vb2_ops = { static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, struct v4l2_pix_format_mplane *dst_fmt) { - unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; - const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); - - src_fmt->pixelformat = src_pix_fmt; - src_fmt->field = V4L2_FIELD_NONE; - src_fmt->flags = 0; - src_fmt->num_planes = src_fmt_info->mem_planes; - wave5_update_pix_fmt(src_fmt, 416, 240); + src_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + wave5_update_pix_fmt(src_fmt, VPU_FMT_TYPE_RAW, + W5_DEF_ENC_PIC_WIDTH, W5_DEF_ENC_PIC_HEIGHT, + &enc_frmsize[VPU_FMT_TYPE_RAW]); dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; - dst_fmt->field = V4L2_FIELD_NONE; - dst_fmt->flags = 0; - dst_fmt->num_planes = 1; - wave5_update_pix_fmt(dst_fmt, 416, 240); + wave5_update_pix_fmt(dst_fmt, VPU_FMT_TYPE_CODEC, + W5_DEF_ENC_PIC_WIDTH, W5_DEF_ENC_PIC_HEIGHT, + &enc_frmsize[VPU_FMT_TYPE_CODEC]); } static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) @@ -1733,6 +1694,8 @@ static int wave5_vpu_open_enc(struct file *filp) v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); + inst->conf_win.width = inst->dst_fmt.width; + inst->conf_win.height = inst->dst_fmt.height; inst->colorspace = V4L2_COLORSPACE_REC709; inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; inst->quantization = V4L2_QUANTIZATION_DEFAULT; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h index 32b7fd3730b5..3847332551fc 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h @@ -38,10 +38,7 @@ enum vpu_fmt_type { struct vpu_format { unsigned int v4l2_pix_fmt; - unsigned int max_width; - unsigned int min_width; - unsigned int max_height; - unsigned int min_height; + const struct v4l2_frmsize_stepwise *v4l2_frmsize; }; static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index e4bc2e467cb5..1ea9f5f31499 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -32,10 +32,29 @@ #define MAX_NUM_INSTANCE 32 -#define W5_MIN_ENC_PIC_WIDTH 256 -#define W5_MIN_ENC_PIC_HEIGHT 128 -#define W5_MAX_ENC_PIC_WIDTH 8192 -#define W5_MAX_ENC_PIC_HEIGHT 8192 +#define W5_DEF_DEC_PIC_WIDTH 720U +#define W5_DEF_DEC_PIC_HEIGHT 480U +#define W5_MIN_DEC_PIC_8_WIDTH 8U +#define W5_MIN_DEC_PIC_8_HEIGHT 8U +#define W5_MIN_DEC_PIC_32_WIDTH 32U +#define W5_MIN_DEC_PIC_32_HEIGHT 32U +#define W5_MAX_DEC_PIC_WIDTH 8192U +#define W5_MAX_DEC_PIC_HEIGHT 4320U +#define W5_DEC_CODEC_STEP_WIDTH 1U +#define W5_DEC_CODEC_STEP_HEIGHT 1U +#define W5_DEC_RAW_STEP_WIDTH 32U +#define W5_DEC_RAW_STEP_HEIGHT 16U + +#define W5_DEF_ENC_PIC_WIDTH 416U +#define W5_DEF_ENC_PIC_HEIGHT 240U +#define W5_MIN_ENC_PIC_WIDTH 256U +#define W5_MIN_ENC_PIC_HEIGHT 128U +#define W5_MAX_ENC_PIC_WIDTH 8192U +#define W5_MAX_ENC_PIC_HEIGHT 8192U +#define W5_ENC_CODEC_STEP_WIDTH 8U +#define W5_ENC_CODEC_STEP_HEIGHT 8U +#define W5_ENC_RAW_STEP_WIDTH 32U +#define W5_ENC_RAW_STEP_HEIGHT 16U // application specific configuration #define VPU_ENC_TIMEOUT 60000 From patchwork Mon Aug 12 07:08:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "jackson.lee" X-Patchwork-Id: 103407 X-Patchwork-Delegate: sebastian.fricke@collabora.com Received: from am.mirrors.kernel.org ([147.75.80.249]) by linuxtv.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sdPBN-0004bR-1K for patchwork@linuxtv.org; Mon, 12 Aug 2024 07:09:35 +0000 Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 24B7B1F22E00 for ; Mon, 12 Aug 2024 07:09:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 58FF4165EFF; Mon, 12 Aug 2024 07:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="ftZ7RQPF" X-Original-To: linux-media@vger.kernel.org Received: from SLXP216CU001.outbound.protection.outlook.com (mail-koreacentralazon11021080.outbound.protection.outlook.com [40.107.42.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A09C165EF7; Mon, 12 Aug 2024 07:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.42.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446532; cv=fail; b=FZqScpvFfR2/cNbx1x+Wz9bo+mUgcpGRymNSqTuzfjKzvdj8IpbLyePLgJ0e6u8NAqasWfx6Y9o8oZhXhocIzmSjlXenxYQuHz36tCnkBL/U6ieTbpRbutPQaqNd+RN3E3f7ZUtsuZaYkVKp0gpyMFU7y+z2rFYIglOkXKUk/4Q= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723446532; c=relaxed/simple; bh=UiTOsuIPdnjFiy25DGycvOoGT0s1iFeQjnnlxcQCqy0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=V4uVfFsCYaTQ/AAxULRq1wrtnVtCZslGYwvw4K3Xgne9FUfHk9ndz4qC32fgSOw7KuKEmKFSHPdoQxCzKcR0gpOTHEcUVzloyRXoVKfdBWAL/YBfgMBEMYQBH3h8BuxuTBhdFb62xTp7NlwLJTGlXtzNRafDBv+825z1zywd/dw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=ftZ7RQPF; arc=fail smtp.client-ip=40.107.42.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fS8lpd47jw3H9NA03pzvH++UTa7NGSrqdBVGRDVi5E06FuJ5phA0naLA9bxX4vvmj4j2zTMHPb5SIU+ZSH2isU35zNU9rkEH//8x+1DgvF6+hUAyubrkgiM2fnmtxWLr+USEeCw+nni0JQVcFOlFcxBwvnQU8eRJshTpT+rqX46pPvLrkt6lcKjQVhrYkr5H/v98AFoPZ8jdHD2k1mECYHqddCATnENU25GGEUxfgEASBJWZksk+361dzwyYW0L7cjIOZT64JGKmRt4/+NqZDkfMs8K0sMYRlR9f1T53ixoAWRdeAR0iV5/JFzMwwBMnR1A2ixCijHUwimoRDk2daw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Jo09o0f7cArhs9nmYI/Ipzy2U9tnqhbP6xrDVuSq5UU=; b=GGyO2DBiXf3CdB7adzxbBOuF/+M1HDGg4Ex+NiafEp7+ASd+Eq89DmY+svf9c/3QP/15+PdtrWXaDGhdpTgMNAMJnJpukWEBcSWcNooG7rYU0TewGa5xSbrBM2MhJymIQ/jMduI+PZXVGr6k1ET6GByRbQdwbr5e4ot0PPNqWNlIW4CLXtFDBXcOPiAjVKtbr5wF2NXipTGMsip4tA67cxREU61Ezqba4bKaYuRFwF88NzaQhAQeLUNpVLxZQyxQLPvfaEstAKthaPD8MAs9BA2MLvUPGijcEHOZdlu96xkIdXKOqzifxkEMwukMDfBcUwLiYOC0FcQSGmPnl/kZtg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Jo09o0f7cArhs9nmYI/Ipzy2U9tnqhbP6xrDVuSq5UU=; b=ftZ7RQPF4l418ZugN9mfsOB1cyiONywFlv9usqDYuiBEJwlZzU32eHSI4JIParzCh9SGDXHN6cWq1kwlIDLPaSxizIdyGgvwYewi5DZyiZmFRH9oT0oRauoJoO3NBhRLH0zbrIECMJSw6/eTCOVqCpmZxnva7RA4kSww+YzgIFI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) by SL2P216MB1530.KORP216.PROD.OUTLOOK.COM (2603:1096:101:33::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 07:08:40 +0000 Received: from SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b]) by SE1P216MB1303.KORP216.PROD.OUTLOOK.COM ([fe80::b711:5ab1:b5a4:d01b%7]) with mapi id 15.20.7849.019; Mon, 12 Aug 2024 07:08:40 +0000 From: "Jackson.lee" To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipsnmedia.com, Nicolas Dufresne Subject: [RESEND PATCH v7 4/4] media: chips-media: wave5: Support YUV422 raw pixel-formats on the encoder. Date: Mon, 12 Aug 2024 16:08:23 +0900 Message-Id: <20240812070823.125-5-jackson.lee@chipsnmedia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812070823.125-1-jackson.lee@chipsnmedia.com> References: <20240812070823.125-1-jackson.lee@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0154.KORP216.PROD.OUTLOOK.COM (2603:1096:101:35::18) To SE1P216MB1303.KORP216.PROD.OUTLOOK.COM (2603:1096:101:15::5) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SE1P216MB1303:EE_|SL2P216MB1530:EE_ X-MS-Office365-Filtering-Correlation-Id: afa22d4b-4c2d-4be7-f0b1-08dcba9d9831 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: SMBxUSIFKSYwGXU/N7uuxppeaK3l92GET8sG7zmPm+4oC/U3/mUtXeSL6ts8MohGOPaz81fj0hj6BgU1hyJjvVnfUAU3D0gl/WFCeh9R6muiLaB1LzWTtwdumc5dIs88pVWUVAOv3oD2d84Hrc2zgYLvNg7clfONx771vfEGxm84lAHeb+DdATWNx1Jpu4VAWmsuasRj3fMyT3d5YOyo3bUS7iACVoD7N4NeeBuav677rbmJ2Mjd4/pj6GGiNilYuOzhCx8WInbpMovStA9Z/xVoNUc3gswRC2c5AXyAhiJ0QI9UqYvdZs2cRpNwXBJzZIrHp/+dAujzx0hoVj+m1di316Arayuc6brHb504yWxAcQzjF2nwYWt/9wllAj+8sVf5jiaE/+hqNKN255x+C8kjL7JCobX/Y8R9qCi/XRn9Po4Qo+lGRhq+Eu0fDzGKFPowTnQIK3GC4jR9gi2fKaE5W+1ApmNldN7DNEg8dQRq/HZX3mxqZbi19/oPqtb86Aty/Y/7O1ChN4viBlj2xtdJLaFT2oL0ZgzcPmDLFuJM9jheg5iZd4M0ERbJHlmug/yArIQPyRAX1PRZOSEIZbZSGCp8cakgmY41OkteFnZElW/kmJknFpTYxXAkVHT7tz3hyBkqXb4rAKEUWkNmL9XIKGunA0lXBujinI5/UjznFpqk/FsoGiQ31wBofi+rjf9XM+yV3pi/TBEMC26LKe8u669Zwx4L2iYSLu9sFWmfiKtdHEzO47HI4IIUNyRStMZtB27XlAGWXRJ2Dp44oRkg7IRVA/RqvdeA6gi4xrfjQtOC/BAAscFNkbiIdNZX0A10OdPFZSRcw87yNv0loXncUHc9HR68Y4SWGYpJZGldqVNXjd1r6qXfvC5wdAL+d9Z5/NyblqSoJFAH2oN3IDVML8h7HicWbRIirvVS3cWIJtaiYiBiFIK9dY4JrPc/6bXpDXhLNxvXu0z529HKuiSdqzmNe4tSf++Ip7pDxLbDmBQ/eteeRcwWljK45KYlh16N9diQ/7RZ+LQK5CJN4rF3573vM3bVyzfv8ndOWsGyM2XBzZoV5sS0XQHzsYgYamdAFB3IVFI4f9N3GPvAQ72H5C2lWFMsQViAJpVPv4Q8VL+kG3KQx02yG8CyWlVHN8Pn+GfV+F/8J9BpqnY6z6EYPNM1BU2xCn705S35GV0QkBoj4ofWSOixUa01QxkXVmPyBUAEuZC4HpujsDAV0YL+ESh+qcx6men7r1fdGU76jutdXg3VLE22cnkvOfvIf54g+ziVM6JSQcGnmsnRGeQqay7T0Y3j+Cle/YM85vVv/0PCNM5OVhTY2RgaeNG8yQMbFGh1RJ1qVCC5JcId3Xf1Kfj5YQeIPOwL60aYvVkz5LfEOUe+7I8Lw7Bmx8qRAoaLKPTU5ahfiR+7g675ZQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SE1P216MB1303.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(52116014)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: q7qXYoImupgLF/9QlngaqbMixYUJZbMvvLxTbqAr2f+bXHsisQFAHr/DQkOAetWbKCfcGuBDmRyl4Kj1dPFpaYyccdLEzezCF9ImxF73/PmUBqG0nfDLxJ9APdoiX1iN6rkx39MbBHbsraXyI1egxLO+4H7Y7CDyJRsFgyEgUuoPq92YiC+p6IvCq2LqF+2sQN0B+qLm9j76Og17yuTkTLaZRUGWQjblE40aKM/ch0CFeok3LGxG0KP0FJXqAKMwN+MqK0e02Vm0qpelrvC9ho8SfwUynLYO/HFY9Wks5usCkljUutofiDgVHfcdVwOWZBtN0AuvA7z46cYG+Kp9a3umMa6Vz989FPh7NezEs+/+g7iIpZUxm/82XSvLa1VTv0QqpXjzf2GdCWRpeYOztof4eOkLW2C9ytcataticfQ207zmP82//zzPDkgMRNPjsfvPy1o5/pGLGqclvQnVn/zJOounq6iO8UXBJvIkYTWV1WTHWmjHFKMzPQfjcjnqjD7vYWo8o6APWTvHnw/EknMbiE64LtDS8Kpj1A89WnqRv778pLPLcuLn2+4JSJeUoXvVmc9+/3kMibtJHAUmfw9xZh0cdhCzIzObi/Z2VT2bPBQA/Yyo6srnp0C2PP0XyBac7izg/8anR+LQpNHwu/bgTwKnMtGYMuF/4eNzua5JrFUG5StgKp1krOt+7h+H5dqVapj5nMCrM4zMBHH2OEFpSqIwNw6dSXAUgB5aVOaveScKJFHkX4o0bEQ4Qt5jNdWUDIhZ5aaH3xw8DnhqnNxWlFKq21Kbuz/TZCKCY1Q/mQImj/urZgbuFx4sGOtH/ZPsGeOPzE4hUCyhtUkYj5/vCu2c2iT+3ByFbg4gfdXPgMIR3D/5mGFDbqDnu3wLkm6BaE2xY/wD6CKxJZp/f02tD+5VSw0y0o2d3mMA33w11252qJgd3a764qeaLOdDiUTiWRb/a+PtT0PlDhcl07tMuaJZeDpKX/z92EUrC3XcYA/9JlsI8Uzb8sBUZdMJI/LKQIPmO9yWMISNQLy8HagySQp9PTAROoNK6+L8jjeVWzfASxkZC11AhtfGzvVUfgst20d/Wr8/loiEz9J76SjJwPMBuk9aMQqAeSpy1XV/SO3LkgafgKWAuKfYn1IaatAcm2QpPNPMO60E0aNUfUOtojhzL4zyH+k5l5ZiVp4rVjYlNxJ1bNSNcMKum0NoYSlUZcJm7WBPvU/GFCyykNisODukQ5oBmR25CHKrjOqz51NXv/kLeOfRkzagglLFTQ2UCUC/RX1mWcT0ez7gpBD0yUyePP/hGhs5ixegDjMFV3WbFhqUIpcYPbIiucQykZN/AxXdHDsyoqLuTQ3AzjX1ynwgPMekuh+IoAR3M5RZ1Ne1b3fyv1ekgX0gMSyfrAySJuEv6eqtSiGyNwlJpCiEbvjh9nBmmMeKzZrpCW6ZpvTzQV/kiib3BHgZOQVBqOtdILYQRYtb36vuqVk183Aoy+J2sxjA6qTZJirO3VqD8pxcx/mioA1KY8MGAEIfAkStQh4EzJqwAm6oa63jGBohaWmFeMywn3ljJCRfIoSvXUQcslja4S95ySLDzDWErURvnDLxeCYy50nxudm5bw== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: afa22d4b-4c2d-4be7-f0b1-08dcba9d9831 X-MS-Exchange-CrossTenant-AuthSource: SE1P216MB1303.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 07:08:40.7731 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: R+1hOwCfD+GM2E+gnmlo6JUD/faDZSo0+lk3ZZNNDUNii7nhHEoiCDMIGh7oJ7p32gHF4Qa12bKGY9nKug4ANHXGPBIxiWwVcGmzAqsmw8k= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB1530 X-LSpam-Score: -6.3 (------) X-LSpam-Report: No, score=-6.3 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DMARC_MISSING=0.001,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_VALIDITY_CERTIFIED=-3,RCVD_IN_VALIDITY_RPBL=1.31,RCVD_IN_VALIDITY_SAFE=-2,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no Add support for the YUV422P, NV16, NV61, YUV422M, NV16M, NV61M raw pixel-formats to the Wave5 encoder. All these formats have a chroma subsampling ratio of 4:2:2 and therefore require a new image size calculation as the driver previously only handled a ratio of 4:2:0. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../chips-media/wave5/wave5-vpu-enc.c | 89 +++++++++++++++---- 1 file changed, 74 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index ef9aa1562346..4e1c8a4e7272 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -66,6 +66,30 @@ static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV16, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV61, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV16M, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV61M, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], + }, } }; @@ -109,13 +133,26 @@ static int start_encode(struct vpu_instance *inst, u32 *fail_res) struct vb2_v4l2_buffer *dst_buf; struct frame_buffer frame_buf; struct enc_param pic_param; - u32 stride = ALIGN(inst->dst_fmt.width, 32); - u32 luma_size = (stride * inst->dst_fmt.height); - u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); + const struct v4l2_format_info *info; + u32 stride = inst->src_fmt.plane_fmt[0].bytesperline; + u32 luma_size = 0; + u32 chroma_size = 0; memset(&pic_param, 0, sizeof(struct enc_param)); memset(&frame_buf, 0, sizeof(struct frame_buffer)); + info = v4l2_format_info(inst->src_fmt.pixelformat); + if (!info) + return -EINVAL; + + if (info->mem_planes == 1) { + luma_size = stride * inst->dst_fmt.height; + chroma_size = luma_size / (info->hdiv * info->vdiv); + } else { + luma_size = inst->src_fmt.plane_fmt[0].sizeimage; + chroma_size = inst->src_fmt.plane_fmt[1].sizeimage; + } + dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx); if (!dst_buf) { dev_dbg(inst->dev->dev, "%s: No destination buffer found\n", __func__); @@ -480,6 +517,7 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form { struct vpu_instance *inst = wave5_to_vpu_inst(fh); const struct vpu_format *vpu_fmt; + const struct v4l2_format_info *info; int i, ret; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", @@ -501,16 +539,20 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; } - if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || - inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { - inst->cbcr_interleave = true; - inst->nv21 = false; - } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || - inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { - inst->cbcr_interleave = true; + info = v4l2_format_info(inst->src_fmt.pixelformat); + if (!info) + return -EINVAL; + + inst->cbcr_interleave = (info->comp_planes == 2) ? true : false; + + switch (inst->src_fmt.pixelformat) { + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_NV61M: inst->nv21 = true; - } else { - inst->cbcr_interleave = false; + break; + default: inst->nv21 = false; } @@ -1095,13 +1137,23 @@ static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) v4l2_m2m_buf_queue(m2m_ctx, vbuf); } -static void wave5_set_enc_openparam(struct enc_open_param *open_param, - struct vpu_instance *inst) +static int wave5_set_enc_openparam(struct enc_open_param *open_param, + struct vpu_instance *inst) { struct enc_wave_param input = inst->enc_param; + const struct v4l2_format_info *info; u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; + info = v4l2_format_info(inst->src_fmt.pixelformat); + if (!info) + return -EINVAL; + + if (info->hdiv == 2 && info->vdiv == 1) + open_param->src_format = FORMAT_422; + else + open_param->src_format = FORMAT_420; + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; open_param->wave_param.hvs_qp_scale = 2; open_param->wave_param.hvs_max_delta_qp = 10; @@ -1190,6 +1242,8 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, open_param->wave_param.intra_refresh_arg = num_ctu_row; } open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable; + + return 0; } static int initialize_sequence(struct vpu_instance *inst) @@ -1285,7 +1339,12 @@ static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count memset(&open_param, 0, sizeof(struct enc_open_param)); - wave5_set_enc_openparam(&open_param, inst); + ret = wave5_set_enc_openparam(&open_param, inst); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_set_enc_openparam, fail: %d\n", + __func__, ret); + goto return_buffers; + } ret = wave5_vpu_enc_open(inst, &open_param); if (ret) {