From patchwork Wed Jun 29 08:27:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Abreu X-Patchwork-Id: 34874 X-Patchwork-Delegate: laurent.pinchart@ideasonboard.com Received: from mail.tu-berlin.de ([130.149.7.33]) by www.linuxtv.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bIAqw-0004B8-Pa; Wed, 29 Jun 2016 08:28:10 +0000 X-tubIT-Incoming-IP: 209.132.180.67 Received: from vger.kernel.org ([209.132.180.67]) by mail.tu-berlin.de (exim-4.84_2/mailfrontend-6) with esmtp id 1bIAqt-0002Jc-5H; Wed, 29 Jun 2016 10:28:09 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750873AbcF2I2E (ORCPT + 1 other); Wed, 29 Jun 2016 04:28:04 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:51045 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750802AbcF2I2D (ORCPT ); Wed, 29 Jun 2016 04:28:03 -0400 Received: from dc8secmta2.synopsys.com (dc8secmta2.synopsys.com [10.13.218.202]) by smtprelay.synopsys.com (Postfix) with ESMTP id CC15710C07F5; Wed, 29 Jun 2016 01:27:51 -0700 (PDT) Received: from dc8secmta2.internal.synopsys.com (dc8secmta2.internal.synopsys.com [127.0.0.1]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id A6C7DA4112; Wed, 29 Jun 2016 01:27:51 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id 7BFD2A4102; Wed, 29 Jun 2016 01:27:51 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 6467F865; Wed, 29 Jun 2016 01:27:51 -0700 (PDT) Received: from synopsys-Macmini.internal.synopsys.com (synopsys-macmini.internal.synopsys.com [10.107.25.47]) by mailhost.synopsys.com (Postfix) with ESMTP id AFCAF862; Wed, 29 Jun 2016 01:27:49 -0700 (PDT) From: Jose Abreu To: linux-media@vger.kernel.org Cc: Jose Abreu , Carlos Palminha , Hyun Kwon , Laurent Pinchart , Mauro Carvalho Chehab Subject: [PATCH] media: platform/xilinx: Set VTC VSYNC/VBLANK values Date: Wed, 29 Jun 2016 09:27:30 +0100 Message-Id: X-Mailer: git-send-email 2.1.4 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-PMX-Version: 6.0.0.2142326, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2016.6.29.81817 X-PMX-Spam: Gauge=IIIIIIII, Probability=8%, Report=' MULTIPLE_RCPTS 0.1, HTML_00_01 0.05, HTML_00_10 0.05, BODYTEXTP_SIZE_3000_LESS 0, BODY_SIZE_2000_2999 0, BODY_SIZE_5000_LESS 0, BODY_SIZE_7000_LESS 0, LEGITIMATE_NEGATE 0, MULTIPLE_RCPTS_RND 0, NO_URI_HTTPS 0, SINGLE_URI_IN_BODY 0, URI_ENDS_IN_HTML 0, __ANY_URI 0, __CP_URI_IN_BODY 0, __FORGED_RCVD_X2_HOST 0, __HAS_CC_HDR 0, __HAS_FROM 0, __HAS_MSGID 0, __HAS_X_MAILER 0, __HAS_X_MAILING_LIST 0, __MIME_TEXT_ONLY 0, __MULTIPLE_RCPTS_CC_X2 0, __SANE_MSGID 0, __SINGLE_URI_TEXT 0, __SUBJ_ALPHA_END 0, __TO_MALFORMED_2 0, __TO_NO_NAME 0, __URI_IN_BODY 0, __URI_NO_WWW 0, __URI_NS , __URI_WITH_PATH 0' This patch sets the values of VSYNC and VBLANK in Xilinx VTC. The patch was tested using a modified version of this driver and using an HDMI compliance equipment. There is still missing the polarity settings for H/V which would require a change in the interface of this driver. Signed-off-by: Jose Abreu Cc: Carlos Palminha Cc: Hyun Kwon Cc: Laurent Pinchart Cc: Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org --- drivers/media/platform/xilinx/xilinx-vtc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/xilinx/xilinx-vtc.c b/drivers/media/platform/xilinx/xilinx-vtc.c index 01c750e..49e82f2 100644 --- a/drivers/media/platform/xilinx/xilinx-vtc.c +++ b/drivers/media/platform/xilinx/xilinx-vtc.c @@ -211,11 +211,15 @@ int xvtc_generator_start(struct xvtc_device *xvtc, xvtc_gen_write(xvtc, XVTC_HSYNC, (config->hsync_end << XVTC_HSYNC_END_SHIFT) | (config->hsync_start << XVTC_HSYNC_START_SHIFT)); - xvtc_gen_write(xvtc, XVTC_F0_VBLANK_H, 0); + xvtc_gen_write(xvtc, XVTC_F0_VBLANK_H, + (config->hsync_start << XVTC_F0_VBLANK_HEND_SHIFT) | + (config->hsync_start << XVTC_F0_VBLANK_HSTART_SHIFT)); xvtc_gen_write(xvtc, XVTC_F0_VSYNC_V, (config->vsync_end << XVTC_F0_VSYNC_VEND_SHIFT) | (config->vsync_start << XVTC_F0_VSYNC_VSTART_SHIFT)); - xvtc_gen_write(xvtc, XVTC_F0_VSYNC_H, 0); + xvtc_gen_write(xvtc, XVTC_F0_VSYNC_H, + (config->hsync_start << XVTC_F0_VSYNC_HEND_SHIFT) | + (config->hsync_start << XVTC_F0_VSYNC_HSTART_SHIFT)); /* Enable the generator. Set the source of all generator parameters to * generator registers.