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Wed, 20 Mar 2024 14:12:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42KEC6LA024002 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Mar 2024 14:12:06 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Mar 2024 07:12:04 -0700 From: Depeng Shao To: , , , , , , CC: , , , Subject: [PATCH v2 4/8] media: qcom: camss: Add new params for csid_device Date: Wed, 20 Mar 2024 19:41:32 +0530 Message-ID: <20240320141136.26827-5-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240320141136.26827-1-quic_depengs@quicinc.com> References: <20240320141136.26827-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qhYRbRXFh6tQz71kNima-LXuIEJERW3Q X-Proofpoint-GUID: qhYRbRXFh6tQz71kNima-LXuIEJERW3Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-20_09,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403200112 X-LSpam-Score: -2.6 (--) X-LSpam-Report: No, score=-2.6 required=5.0 tests=ARC_SIGNED=0.001,ARC_VALID=-0.1,BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,DMARC_PASS=-0.001,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_NONE=-0.0001,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no CSID gen3 has a new register block which is named as CSID top, it controls the output of CSID, since the CSID can connect to SFE or original VFE in CSID gen3. The register update is moved to CSID from VFE in CSID gen3. So, adding top_base and reg_update variables in csid device structure for CSID gen3. Signed-off-by: Depeng Shao --- drivers/media/platform/qcom/camss/camss-csid.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 4a9e5a2d1f92..ca654b007441 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -162,7 +162,9 @@ struct csid_device { struct v4l2_subdev subdev; struct media_pad pads[MSM_CSID_PADS_NUM]; void __iomem *base; + void __iomem *top_base; u32 irq; + u32 reg_update; char irq_name[30]; struct camss_clock *clock; int nclocks;