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Lin" , Singo Chang , Nancy Lin , Shawn Sung , Subject: [PATCH v3 4/9] soc: mediatek: cmdq: Add cmdq_pkt_write_s_reg_value to support write value to reg Date: Fri, 22 Dec 2023 12:52:23 +0800 Message-ID: <20231222045228.27826-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231222045228.27826-1-jason-jh.lin@mediatek.com> References: <20231222045228.27826-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.192500-8.000000 X-TMASE-MatchedRID: k8Cd32tj8sFvH7GZAcw0g8nUT+eskUQPLoYOuiLW+uU06dhcpwNHEBFx R5JQAS6O09NQNrxIpFYQ5m8HWfjjn5/1JE49xL3GaUe/i9AephOlAfiiC1VA/aUIR8WYCZ8yo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtSjEbty+5RAw3D5+9hEAfnqdHW2GAcBekaA/4J+I0pB6tRT 0UuGYQUzfmXwixG2Ih7CbXtL4xRRJ83aVkj2fp76V2chaMw8OHwZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5QBJtcKcOYfpRMZUCEHkRt X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.192500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7665CB8DB71DB0D075B3BF58E3AF737164242C705814F4F76513766263AE46EF2000:8 X-MTK: N X-LSpam-Score: -4.8 (----) X-LSpam-Report: No, score=-4.8 required=5.0 tests=BAYES_00=-1.9,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1,RCVD_IN_DNSWL_MED=-2.3,UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no Add cmdq_pkt_write_s_reg_value to support write a value to a register. It appends write_s command to the command buffer in a CMDQ packet, ask GCE to excute a write instruction to write a value to a register with low 16 bits physical address offset. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 60f8ecbab5e7..dfef436d9b8a 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -287,6 +287,19 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, } EXPORT_SYMBOL(cmdq_pkt_write_s_value); +int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value) +{ + struct cmdq_instruction inst = {}; + + inst.op = CMDQ_CODE_WRITE_S; + inst.dst_t = CMDQ_REG_TYPE; + inst.reg_dst = high_addr_reg_idx; + inst.value = value; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_write_s_reg_value); + int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask) { diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 73eadda1dd2d..d1cd8108cad0 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -208,6 +208,17 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask); +/** + * cmdq_pkt_write_s_reg_value() - append write_s command to the CMDQ packet which + * write value to a register with low address pa + * @pkt: the CMDQ packet + * @high_addr_reg_idx: internal register ID which contains high address of pa + * @value: the specified target value + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet