[RFC,V2,3/6] dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support
Commit Message
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Introducing the G2 hevc video decoder requires modifications of the bindings to allow
one node per VPU.
VPUs share one hardware control block which is provided as a phandle on
a syscon.
Each node has now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be compatible with older DT the driver is still capable to use the 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Comments
On Mon, 06 Dec 2021 19:54:42 -0600, Adam Ford wrote:
> From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>
> Introducing the G2 hevc video decoder requires modifications of the bindings to allow
> one node per VPU.
>
> VPUs share one hardware control block which is provided as a phandle on
> a syscon.
> Each node has now one reg and one interrupt.
> Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
>
> To be compatible with older DT the driver is still capable to use the 'ctrl'
> reg-name even if it is deprecated now.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml: properties:clock-names:oneOf: [{'const': 'g1'}, {'const': 'g2'}] should not be valid under {'items': {'propertyNames': {'const': 'const'}, 'required': ['const']}}
hint: Use 'enum' rather than 'oneOf' + 'const' entries
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml: properties:interrupt-names:oneOf: [{'const': 'g1'}, {'const': 'g2'}] should not be valid under {'items': {'propertyNames': {'const': 'const'}, 'required': ['const']}}
hint: Use 'enum' rather than 'oneOf' + 'const' entries
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml: properties:compatible:oneOf: [{'const': 'nxp,imx8mq-vpu-g1'}, {'const': 'nxp,imx8mq-vpu-g2'}] should not be valid under {'items': {'propertyNames': {'const': 'const'}, 'required': ['const']}}
hint: Use 'enum' rather than 'oneOf' + 'const' entries
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml: ignoring, error in schema: properties: interrupt-names: oneOf
warning: no schema found in file: ./Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
Error: Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.example.dts:26.27-31 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1564457
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Mon, Dec 06, 2021 at 07:54:42PM -0600, Adam Ford wrote:
> From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>
> Introducing the G2 hevc video decoder requires modifications of the bindings to allow
> one node per VPU.
Why? It looks like the G2 part was already described. If you are
changing this because you want 2 drivers for G1 and G2, then NAK. DT
nodes and drivers don't have to be 1:1. This change is breaking
compatibility.
>
> VPUs share one hardware control block which is provided as a phandle on
> a syscon.
That's not really ideal. Is this really a separate block?
> Each node has now one reg and one interrupt.
> Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
>
> To be compatible with older DT the driver is still capable to use the 'ctrl'
> reg-name even if it is deprecated now.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> index 762be3f96ce9..eaeba4ce262a 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -15,37 +15,36 @@ description:
>
> properties:
> compatible:
> - const: nxp,imx8mq-vpu
> + oneOf:
> + - const: nxp,imx8mq-vpu-g1
> + - const: nxp,imx8mq-vpu-g2
>
> reg:
> - maxItems: 3
> -
> - reg-names:
> - items:
> - - const: g1
> - - const: g2
> - - const: ctrl
> + maxItems: 1
>
> interrupts:
> - maxItems: 2
> + maxItems: 1
>
> interrupt-names:
> - items:
> + oneOf:
> - const: g1
> - const: g2
>
> clocks:
> - maxItems: 3
> + maxItems: 1
>
> clock-names:
> - items:
> + oneOf:
> - const: g1
> - const: g2
> - - const: bus
>
> power-domains:
> maxItems: 1
>
> + nxp,imx8m-vpu-ctrl:
> + description: Specifies a phandle to syscon VPU hardware control block
> + $ref: "/schemas/types.yaml#/definitions/phandle"
This is optional?
> +
> required:
> - compatible
> - reg
> @@ -60,20 +59,27 @@ additionalProperties: false
> examples:
> - |
> #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - vpu: video-codec@38300000 {
> + vpu_g1: video-codec@38300000 {
> compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> - clock-names = "g1", "g2", "bus";
> - power-domains = <&pgc_vpu>;
> + reg = <0x38300000 0x10000>;
> + reg-names "g1";
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "g1";
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + clock-names = "g1";
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38300000 0x10000>;
> + reg-names "g2";
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "g2";
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + clock-names = "g2";
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> };
> --
> 2.32.0
>
>
Hi Rob,
Am Dienstag, dem 07.12.2021 um 09:14 -0600 schrieb Rob Herring:
> On Mon, Dec 06, 2021 at 07:54:42PM -0600, Adam Ford wrote:
> > From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> >
> > Introducing the G2 hevc video decoder requires modifications of the bindings to allow
> > one node per VPU.
>
> Why? It looks like the G2 part was already described. If you are
> changing this because you want 2 drivers for G1 and G2, then NAK. DT
> nodes and drivers don't have to be 1:1. This change is breaking
> compatibility.
We can keep the compatibility by just keeping the code in the VPU
driver to handle the G1 block as-is. The VPU block on the imx8mq is
really three peripherals: the control block working together with the
power domain controller to provide clocks and resets and the G1 and G2
VPU cores.
>
> >
> > VPUs share one hardware control block which is provided as a phandle on
> > a syscon.
>
> That's not really ideal. Is this really a separate block?
>
This part of the commit message is not accurate anymore. The control
block is in fact so separate from the VPU that we even added a new
driver to handle those control blocks: the imx8m blk-ctrl driver. The
VPU driver doesn't need handle this control block anymore, it's now
handled via the power-domain abstraction.
Regards,
Lucas
> > Each node has now one reg and one interrupt.
> > Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
> >
> > To be compatible with older DT the driver is still capable to use the 'ctrl'
> > reg-name even if it is deprecated now.
> >
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
> > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > index 762be3f96ce9..eaeba4ce262a 100644
> > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > @@ -15,37 +15,36 @@ description:
> >
> > properties:
> > compatible:
> > - const: nxp,imx8mq-vpu
> > + oneOf:
> > + - const: nxp,imx8mq-vpu-g1
> > + - const: nxp,imx8mq-vpu-g2
> >
> > reg:
> > - maxItems: 3
> > -
> > - reg-names:
> > - items:
> > - - const: g1
> > - - const: g2
> > - - const: ctrl
> > + maxItems: 1
> >
> > interrupts:
> > - maxItems: 2
> > + maxItems: 1
> >
> > interrupt-names:
> > - items:
> > + oneOf:
> > - const: g1
> > - const: g2
> >
> > clocks:
> > - maxItems: 3
> > + maxItems: 1
> >
> > clock-names:
> > - items:
> > + oneOf:
> > - const: g1
> > - const: g2
> > - - const: bus
> >
> > power-domains:
> > maxItems: 1
> >
> > + nxp,imx8m-vpu-ctrl:
> > + description: Specifies a phandle to syscon VPU hardware control block
> > + $ref: "/schemas/types.yaml#/definitions/phandle"
>
> This is optional?
>
> > +
> > required:
> > - compatible
> > - reg
> > @@ -60,20 +59,27 @@ additionalProperties: false
> > examples:
> > - |
> > #include <dt-bindings/clock/imx8mq-clock.h>
> > + #include <dt-bindings/power/imx8mq-power.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> >
> > - vpu: video-codec@38300000 {
> > + vpu_g1: video-codec@38300000 {
> > compatible = "nxp,imx8mq-vpu";
> > - reg = <0x38300000 0x10000>,
> > - <0x38310000 0x10000>,
> > - <0x38320000 0x10000>;
> > - reg-names = "g1", "g2", "ctrl";
> > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "g1", "g2";
> > - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > - clock-names = "g1", "g2", "bus";
> > - power-domains = <&pgc_vpu>;
> > + reg = <0x38300000 0x10000>;
> > + reg-names "g1";
> > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "g1";
> > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > + clock-names = "g1";
> > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> > + };
> > +
> > + vpu_g2: video-codec@38310000 {
> > + compatible = "nxp,imx8mq-vpu-g2";
> > + reg = <0x38300000 0x10000>;
> > + reg-names "g2";
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "g2";
> > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > + clock-names = "g2";
> > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> > };
> > --
> > 2.32.0
> >
> >
@@ -15,37 +15,36 @@ description:
properties:
compatible:
- const: nxp,imx8mq-vpu
+ oneOf:
+ - const: nxp,imx8mq-vpu-g1
+ - const: nxp,imx8mq-vpu-g2
reg:
- maxItems: 3
-
- reg-names:
- items:
- - const: g1
- - const: g2
- - const: ctrl
+ maxItems: 1
interrupts:
- maxItems: 2
+ maxItems: 1
interrupt-names:
- items:
+ oneOf:
- const: g1
- const: g2
clocks:
- maxItems: 3
+ maxItems: 1
clock-names:
- items:
+ oneOf:
- const: g1
- const: g2
- - const: bus
power-domains:
maxItems: 1
+ nxp,imx8m-vpu-ctrl:
+ description: Specifies a phandle to syscon VPU hardware control block
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
required:
- compatible
- reg
@@ -60,20 +59,27 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
+ #include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- vpu: video-codec@38300000 {
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
- clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
- <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
- clock-names = "g1", "g2", "bus";
- power-domains = <&pgc_vpu>;
+ reg = <0x38300000 0x10000>;
+ reg-names "g1";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+ clock-names = "g1";
+ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38300000 0x10000>;
+ reg-names "g2";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+ clock-names = "g2";
+ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
};