From patchwork Thu Jul 16 17:18:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Prabhakar Mahadev Lad X-Patchwork-Id: 65575 Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from ) id 1jw7Tl-0002dv-Ju; Thu, 16 Jul 2020 17:15:30 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729804AbgGPRU2 (ORCPT + 1 other); Thu, 16 Jul 2020 13:20:28 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:5757 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729323AbgGPRU1 (ORCPT ); Thu, 16 Jul 2020 13:20:27 -0400 X-IronPort-AV: E=Sophos;i="5.75,360,1589209200"; d="scan'208";a="52319184" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Jul 2020 02:20:24 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E209540B5640; Fri, 17 Jul 2020 02:20:19 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Jens Axboe , Rob Herring , Vinod Koul , Mauro Carvalho Chehab , Marek Vasut , Yoshihiro Shimoda , Mark Brown , Niklas , Bjorn Helgaas , Kishon Vijay Abraham I , Liam Girdwood , Greg Kroah-Hartman , Magnus Damm , devicetree@vger.kernel.org Cc: linux-ide@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-pci@vger.kernel.org, alsa-devel@alsa-project.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, Prabhakar , Lad Prabhakar Subject: [PATCH 19/20] media: rcar-vin: Enable support for R8A774E1 Date: Thu, 16 Jul 2020 18:18:34 +0100 Message-Id: <1594919915-5225-20-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594919915-5225-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <1594919915-5225-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.4 (--) X-LSpam-Report: No, score=-2.4 required=5.0 tests=BAYES_00=-1.9,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no Add the SoC specific information for RZ/G2H (R8A774E1) SoC. Also add the routing information between CSI2 and VIN (which is similar to R-Car H3 except it lacks CSI41). Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Niklas Söderlund --- drivers/media/platform/rcar-vin/rcar-core.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index 7440c8965d27..4fb76d1df308 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -944,6 +944,42 @@ static const struct rvin_info rcar_info_gen2 = { .max_height = 2048, }; +static const struct rvin_group_route rcar_info_r8a774e1_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, + { /* Sentinel */ } +}; + +static const struct rvin_info rcar_info_r8a774e1 = { + .model = RCAR_GEN3, + .use_mc = true, + .max_width = 4096, + .max_height = 4096, + .routes = rcar_info_r8a774e1_routes, +}; + static const struct rvin_group_route rcar_info_r8a7795_routes[] = { { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, @@ -1220,6 +1256,10 @@ static const struct of_device_id rvin_of_id_table[] = { .compatible = "renesas,vin-r8a774c0", .data = &rcar_info_r8a77990, }, + { + .compatible = "renesas,vin-r8a774e1", + .data = &rcar_info_r8a774e1, + }, { .compatible = "renesas,vin-r8a7778", .data = &rcar_info_m1,