media: ipu3.rst: add yuv-downscaling into pipeline diagram

Message ID 1585659640-10049-1-git-send-email-bingbu.cao@intel.com (mailing list archive)
State Under Review, archived
Delegated to: Sakari Ailus
Headers
Series media: ipu3.rst: add yuv-downscaling into pipeline diagram |

Commit Message

Cao, Bingbu March 31, 2020, 1 p.m. UTC
  For ipu3 ImgU image processing, the frame data from TNR can feed into
DDR by Output Formatting System or feed into YUV downscaler to do YUV
downscaling for secondary output, which is usually used for display.
current ImgU image pipeline diagram misses the YUV downscaling,
this patch add it to aligh with actual hardware blocks.

Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 Documentation/media/v4l-drivers/ipu3.rst | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)
  

Patch

diff --git a/Documentation/media/v4l-drivers/ipu3.rst b/Documentation/media/v4l-drivers/ipu3.rst
index a694f49491f9..c200cb5fc91b 100644
--- a/Documentation/media/v4l-drivers/ipu3.rst
+++ b/Documentation/media/v4l-drivers/ipu3.rst
@@ -429,16 +429,16 @@  set of parameters as input. The major stages of pipelines are shown here:
        o [label="Total Color Correction"]
        p [label="XNR3"]
        q [label="TNR"]
-       r [label="DDR"]
+       r [label="DDR", style=filled, fillcolor=yellow, shape=cylinder]
+       s [label="YUV Downscaling"]
+       t [label="DDR", style=filled, fillcolor=yellow, shape=cylinder]
 
-       { rank=same; a -> b -> c -> d -> e -> f }
-       { rank=same; g -> h -> i -> j -> k -> l }
-       { rank=same; m -> n -> o -> p -> q -> r }
+       { rank=same; a -> b -> c -> d -> e -> f -> g -> h -> i }
+       { rank=same; j -> k -> l -> m -> n -> o -> p -> q -> s -> t}
 
-       a -> g -> m [style=invis, weight=10]
-
-       f -> g
-       l -> m
+       a -> j [style=invis, weight=10]
+       i -> j
+       q -> r
    }
 
 The table below presents a description of the above algorithms.