From patchwork Thu Sep 27 14:46:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues FRUCHET X-Patchwork-Id: 52254 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([209.132.180.67]) by www.linuxtv.org with esmtp (Exim 4.84_2) (envelope-from ) id 1g5XYn-0003Ll-U8; Thu, 27 Sep 2018 14:46:34 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeI0VFF (ORCPT + 1 other); Thu, 27 Sep 2018 17:05:05 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:18362 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727522AbeI0VFF (ORCPT ); Thu, 27 Sep 2018 17:05:05 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8REdMXF004439; Thu, 27 Sep 2018 16:46:17 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2mqd47ry70-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 27 Sep 2018 16:46:17 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 41BD638; Thu, 27 Sep 2018 14:46:17 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 19F634E0C; Thu, 27 Sep 2018 14:46:17 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 27 Sep 2018 16:46:17 +0200 Received: from localhost (10.201.23.73) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 27 Sep 2018 16:46:16 +0200 From: Hugues Fruchet To: Steve Longerbeam , Sakari Ailus , Hans Verkuil , "Mauro Carvalho Chehab" , Rob Herring , Mark Rutland , Maxime Ripard CC: , , , Hugues Fruchet , Benjamin Gaignard , Jacopo Mondi Subject: [PATCH 4/4] media: ov5640: reduce rate according to maximum pixel clock frequency Date: Thu, 27 Sep 2018 16:46:07 +0200 Message-ID: <1538059567-8381-5-git-send-email-hugues.fruchet@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538059567-8381-1-git-send-email-hugues.fruchet@st.com> References: <1538059567-8381-1-git-send-email-hugues.fruchet@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.73] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-27_07:, , signatures=0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Reduce parallel port rate according to maximum pixel clock frequency admissible by camera interface. This allows to support any resolutions/framerate requests by decreasing the framerate according to maximum camera interface capabilities. Signed-off-by: Hugues Fruchet --- drivers/media/i2c/ov5640.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index da4d754..9f3c32e 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -918,6 +918,8 @@ static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, { u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div; int ret; + struct i2c_client *client = sensor->i2c_client; + unsigned int pclk_freq, max_pclk_freq; /* * FIXME, value of PCLK divider deduced from * mode registers hardcoded sequence and tests @@ -941,6 +943,16 @@ static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, if (ret) return ret; + pclk_freq = rate / dvp_pclk_divider; + max_pclk_freq = sensor->ep.bus.parallel.pclk_max_frequency; + + /* clip rate according to optional maximum pixel clock limit */ + if (max_pclk_freq && pclk_freq > max_pclk_freq) { + rate = max_pclk_freq * dvp_pclk_divider; + dev_dbg(&client->dev, "DVP pixel clock too high (%d > %d Hz), reducing rate...\n", + pclk_freq, max_pclk_freq); + } + ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv, &bit_div, &pclk_div);