From patchwork Thu Sep 27 14:46:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues FRUCHET X-Patchwork-Id: 52251 X-Patchwork-Delegate: sakari.ailus@iki.fi Received: from vger.kernel.org ([209.132.180.67]) by www.linuxtv.org with esmtp (Exim 4.84_2) (envelope-from ) id 1g5XYk-0003Ll-TU; Thu, 27 Sep 2018 14:46:31 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727588AbeI0VFC (ORCPT + 1 other); Thu, 27 Sep 2018 17:05:02 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:16209 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727307AbeI0VFC (ORCPT ); Thu, 27 Sep 2018 17:05:02 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8REd1LY009405; Thu, 27 Sep 2018 16:46:15 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2mnb6xugrr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 27 Sep 2018 16:46:15 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 24C7234; Thu, 27 Sep 2018 14:46:15 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 054DD4E0A; Thu, 27 Sep 2018 14:46:15 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 27 Sep 2018 16:46:14 +0200 Received: from localhost (10.201.23.73) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 27 Sep 2018 16:46:14 +0200 From: Hugues Fruchet To: Steve Longerbeam , Sakari Ailus , Hans Verkuil , "Mauro Carvalho Chehab" , Rob Herring , Mark Rutland , Maxime Ripard CC: , , , Hugues Fruchet , Benjamin Gaignard , Jacopo Mondi Subject: [PATCH 2/4] media: v4l2-core: add pixel clock max frequency parallel port property Date: Thu, 27 Sep 2018 16:46:05 +0200 Message-ID: <1538059567-8381-3-git-send-email-hugues.fruchet@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538059567-8381-1-git-send-email-hugues.fruchet@st.com> References: <1538059567-8381-1-git-send-email-hugues.fruchet@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.73] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-27_07:, , signatures=0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add pclk-max-frequency property in parallel port endpoint in order to inform sensor of the maximum pixel clock frequency admissible by camera interface that is connected on. Signed-off-by: Hugues Fruchet --- drivers/media/v4l2-core/v4l2-fwnode.c | 3 +++ include/media/v4l2-fwnode.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 169bdbb..505338e 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -158,6 +158,9 @@ static void v4l2_fwnode_endpoint_parse_parallel_bus( flags |= v ? V4L2_MBUS_DATA_ENABLE_HIGH : V4L2_MBUS_DATA_ENABLE_LOW; + if (!fwnode_property_read_u32(fwnode, "pclk-max-frequency", &v)) + bus->pclk_max_frequency = v; + bus->flags = flags; } diff --git a/include/media/v4l2-fwnode.h b/include/media/v4l2-fwnode.h index 9cccab6..946b48d 100644 --- a/include/media/v4l2-fwnode.h +++ b/include/media/v4l2-fwnode.h @@ -52,11 +52,13 @@ struct v4l2_fwnode_bus_mipi_csi2 { * @flags: media bus (V4L2_MBUS_*) flags * @bus_width: bus width in bits * @data_shift: data shift in bits + * @max_pclk_frequency: maximum pixel clock in hertz */ struct v4l2_fwnode_bus_parallel { unsigned int flags; unsigned char bus_width; unsigned char data_shift; + unsigned int pclk_max_frequency; }; /**