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[31.51.85.245]) by smtp.gmail.com with ESMTPSA id lr9sm7124002wjb.39.2016.06.09.06.41.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jun 2016 06:41:40 -0700 (PDT) From: Kieran Bingham To: Kieran Bingham , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-media@vger.kernel.org (open list:MEDIA DRIVERS FOR RENESAS - FDP1), linux-renesas-soc@vger.kernel.org (open list:MEDIA DRIVERS FOR RENESAS - FDP1), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/3] dt-bindings: Add Renesas R-Car FDP1 bindings Date: Thu, 9 Jun 2016 14:41:34 +0100 Message-Id: <1465479695-18644-4-git-send-email-kieran@bingham.xyz> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1465479695-18644-1-git-send-email-kieran@bingham.xyz> References: <1465479695-18644-1-git-send-email-kieran@bingham.xyz> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-PMX-Version: 6.0.0.2142326, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2016.6.9.133617 X-PMX-Spam: Gauge=IIIIIIIII, Probability=9%, Report=' MULTIPLE_RCPTS 0.1, XYZ_TLD 0.1, HTML_00_01 0.05, HTML_00_10 0.05, BODYTEXTP_SIZE_3000_LESS 0, BODY_SIZE_2000_2999 0, BODY_SIZE_5000_LESS 0, BODY_SIZE_7000_LESS 0, CS_SUSP_TLD_BODY 0, DKIM_SIGNATURE 0, IN_REP_TO 0, LEGITIMATE_NEGATE 0, MSG_THREAD 0, MULTIPLE_RCPTS_RND 0, NO_URI_HTTPS 0, REFERENCES 0, SINGLE_URI_IN_BODY 0, URI_ENDS_IN_HTML 0, __ANY_URI 0, __CP_MEDIA_BODY 0, __CP_URI_IN_BODY 0, __HAS_FROM 0, __HAS_MSGID 0, __HAS_X_MAILER 0, __HAS_X_MAILING_LIST 0, __IN_REP_TO 0, __MIME_TEXT_ONLY 0, __MULTIPLE_RCPTS_TO_X5 0, __REFERENCES 0, __SANE_MSGID 0, __SINGLE_URI_TEXT 0, __SUBJ_ALPHA_END 0, __TO_MALFORMED_2 0, __URI_IN_BODY 0, __URI_NO_WWW 0, __URI_NS , __URI_WITH_PATH 0, __YOUTUBE_RCVD 0' The FDP1 is a de-interlacing module which converts interlaced video to progressive video. It is also capable of performing pixel format conversion between YCbCr/YUV formats and RGB formats. Signed-off-by: Kieran Bingham --- .../devicetree/bindings/media/renesas,fdp1.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/renesas,fdp1.txt diff --git a/Documentation/devicetree/bindings/media/renesas,fdp1.txt b/Documentation/devicetree/bindings/media/renesas,fdp1.txt new file mode 100644 index 000000000000..e2da2aec5e9f --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,fdp1.txt @@ -0,0 +1,34 @@ +Renesas R-Car Fine Display Processor (FDP1) +----------------------------------------------- + +The FDP1 is a de-interlacing module which converts interlaced video to +progressive video. It is capable of performing pixel format conversion between +YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as +an input to the module. + + - compatible: Must be one or more of the following + + - "renesas,r8a7795-fdp1" for R8A7795 (R-Car H3) + - "renesas,r8a7796-fdp1" for R8A7796 (R-Car M3-W) + - "renesas,fdp1" for generic compatible + + When compatible with the generic version, nodes must list the + SoC-specific version corresponding to the platform first, followed by the + family-specific and/or generic versions. + + - reg: the register base and size for the device registers + - clocks: Reference to the functional clock + - renesas,fcp: Reference to the FCPF connected to the FDP1 + + +Device node example +------------------- + + fdp1ch1: fdp1@fe940000 { + compatible = "renesas,r8a7795-fdp1", "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf0>; + }; \ No newline at end of file