From patchwork Tue Aug 4 09:37:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Wu X-Patchwork-Id: 30761 X-Patchwork-Delegate: g.liakhovetski@gmx.de Received: from mail.tu-berlin.de ([130.149.7.33]) by www.linuxtv.org with esmtp (Exim 4.72) (envelope-from ) id 1ZMYac-0000MY-PD; Tue, 04 Aug 2015 11:32:54 +0200 X-tubIT-Incoming-IP: 209.132.180.67 Received: from vger.kernel.org ([209.132.180.67]) by mail.tu-berlin.de (exim-4.76/mailfrontend-7) with esmtp id 1ZMYaa-0003KY-3D; Tue, 04 Aug 2015 11:32:54 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932456AbbHDJcu (ORCPT + 1 other); Tue, 4 Aug 2015 05:32:50 -0400 Received: from nasmtp01.atmel.com ([192.199.1.245]:14079 "EHLO DVREDG01.corp.atmel.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932179AbbHDJct (ORCPT ); Tue, 4 Aug 2015 05:32:49 -0400 Received: from apsmtp01.atmel.com (10.168.254.31) by DVREDG01.corp.atmel.com (10.42.103.30) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 4 Aug 2015 03:32:45 -0600 Received: from melon.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com (10.168.254.31) with Microsoft SMTP Server id 14.3.235.1; Tue, 4 Aug 2015 17:33:21 +0800 From: Josh Wu To: Linux Media Mailing List , "Guennadi Liakhovetski" , CC: Laurent Pinchart , Josh Wu Subject: [PATCH v3] media: atmel-isi: parse the DT parameters for vsync/hsync/pixclock polarity Date: Tue, 4 Aug 2015 17:37:49 +0800 Message-ID: <1438681069-16981-1-git-send-email-josh.wu@atmel.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-PMX-Version: 6.0.0.2142326, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2015.8.4.92716 X-PMX-Spam: Gauge=IIIIIIIII, Probability=9%, Report=' MULTIPLE_RCPTS 0.1, HTML_00_01 0.05, HTML_00_10 0.05, MSGID_ADDED_BY_MTA 0.05, BODYTEXTP_SIZE_3000_LESS 0, BODY_SIZE_1900_1999 0, BODY_SIZE_2000_LESS 0, BODY_SIZE_5000_LESS 0, BODY_SIZE_7000_LESS 0, NO_URI_HTTPS 0, SINGLE_URI_IN_BODY 0, URI_ENDS_IN_HTML 0, __ANY_URI 0, __CP_MEDIA_BODY 0, __CP_POSSIBLE_EXPLOIT_SUBJ 0, __CP_URI_IN_BODY 0, __CT 0, __CT_TEXT_PLAIN 0, __DATE_TZ_HK 0, __HAS_FROM 0, __HAS_MSGID 0, __HAS_X_MAILER 0, __HAS_X_MAILING_LIST 0, __MIME_TEXT_ONLY 0, __MIME_VERSION 0, __MULTIPLE_RCPTS_CC_X2 0, __SANE_MSGID 0, __SUBJ_ALPHA_END 0, __TO_MALFORMED_2 0, __URI_IN_BODY 0, __URI_NO_WWW 0, __URI_NS ' This patch will get the DT parameters of vsync/hsync/pixclock polarity, and pass to driver. Also add a debug information for test purpose. Signed-off-by: Josh Wu Reviewed-by: Laurent Pinchart --- Changes in v3: - add embedded sync dt property support. Changes in v2: - rewrite the debug message and add pix clock polarity setup thanks to Laurent. - update the commit log. drivers/media/platform/soc_camera/atmel-isi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c index fead841..4efc939 100644 --- a/drivers/media/platform/soc_camera/atmel-isi.c +++ b/drivers/media/platform/soc_camera/atmel-isi.c @@ -1061,6 +1061,11 @@ static int isi_camera_set_bus_param(struct soc_camera_device *icd) if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING; + dev_dbg(icd->parent, "vsync active %s, hsync active %s, sampling on pix clock %s edge\n", + common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? "low" : "high", + common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? "low" : "high", + common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING ? "falling" : "rising"); + if (isi->pdata.has_emb_sync) cfg1 |= ISI_CFG1_EMB_SYNC; if (isi->pdata.full_mode) @@ -1148,6 +1153,16 @@ static int atmel_isi_parse_dt(struct atmel_isi *isi, return -EINVAL; } + if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + isi->pdata.hsync_act_low = true; + if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + isi->pdata.vsync_act_low = true; + if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) + isi->pdata.pclk_act_falling = true; + + if (ep.bus_type == V4L2_MBUS_BT656) + isi->pdata.has_emb_sync = true; + return 0; }