From patchwork Fri Sep 16 06:39:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 352 Return-path: Envelope-to: mchehab@canuck.infradead.org Delivery-date: Fri, 16 Sep 2011 06:37:58 +0000 Received: from canuck.infradead.org [134.117.69.58] by localhost.localdomain with IMAP (fetchmail-6.3.20) for (single-drop); Fri, 16 Sep 2011 07:53:26 -0300 (BRT) Received: from casper.infradead.org ([2001:770:15f::2]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R4S3i-0008U3-1T for mchehab@canuck.infradead.org; Fri, 16 Sep 2011 06:37:58 +0000 Received: from vger.kernel.org ([209.132.180.67]) by casper.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R4S3e-0003D4-9a; Fri, 16 Sep 2011 06:37:56 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752714Ab1IPGht (ORCPT + 1 other); Fri, 16 Sep 2011 02:37:49 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:37243 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750788Ab1IPGhs (ORCPT ); Fri, 16 Sep 2011 02:37:48 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p8G6bmQn006335 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 16 Sep 2011 01:37:48 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id p8G6blaQ012808; Fri, 16 Sep 2011 01:37:47 -0500 (CDT) Received: from DLEE74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p8G6blx2024341; Fri, 16 Sep 2011 01:37:47 -0500 (CDT) Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Fri, 16 Sep 2011 01:37:48 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id p8G6bluB029603; Fri, 16 Sep 2011 01:37:47 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.137.144]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id p8G6bj023595; Fri, 16 Sep 2011 01:37:45 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja , , Lajos Molnar Subject: [PATCH v2 1/3] OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting Date: Fri, 16 Sep 2011 12:09:11 +0530 Message-ID: <1316155153-24351-2-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1316155153-24351-1-git-send-email-archit@ti.com> References: <1316155153-24351-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110916_073754_860425_5760646C X-CRM114-Status: GOOD ( 24.95 ) X-Spam-Score: -2.2 (--) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-2.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [209.132.180.67 listed in list.dnswl.org] 2.8 KB_DATE_CONTAINS_TAB KB_DATE_CONTAINS_TAB 2.5 TAB_IN_FROM From starts with a tab -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipleine attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled int the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Initial patch was made by: Lajos Molnar Cc: linux-media@vger.kernel.org Cc: Lajos Molnar Signed-off-by: Archit Taneja --- drivers/media/video/omap/omap_vout.c | 16 +++++++++++----- drivers/video/omap2/dss/dispc.c | 24 ++++++++++++------------ drivers/video/omap2/dss/dss.h | 4 ++-- drivers/video/omap2/dss/dss_features.c | 22 +++++++++++----------- drivers/video/omap2/dss/dss_features.h | 3 ++- drivers/video/omap2/dss/manager.c | 28 +++++++++++++++++++--------- include/video/omapdss.h | 3 ++- 7 files changed, 59 insertions(+), 41 deletions(-) diff --git a/drivers/media/video/omap/omap_vout.c b/drivers/media/video/omap/omap_vout.c index b3a5ecd..95daf98 100644 --- a/drivers/media/video/omap/omap_vout.c +++ b/drivers/media/video/omap/omap_vout.c @@ -1165,12 +1165,17 @@ static int vidioc_try_fmt_vid_overlay(struct file *file, void *fh, { int ret = 0; struct omap_vout_device *vout = fh; + struct omap_overlay *ovl; + struct omapvideo_info *ovid; struct v4l2_window *win = &f->fmt.win; + ovid = &vout->vid_info; + ovl = ovid->overlays[0]; + ret = omap_vout_try_window(&vout->fbuf, win); if (!ret) { - if (vout->vid == OMAP_VIDEO1) + if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) win->global_alpha = 255; else win->global_alpha = f->fmt.win.global_alpha; @@ -1194,8 +1199,7 @@ static int vidioc_s_fmt_vid_overlay(struct file *file, void *fh, ret = omap_vout_new_window(&vout->crop, &vout->win, &vout->fbuf, win); if (!ret) { - /* Video1 plane does not support global alpha */ - if (ovl->id == OMAP_DSS_VIDEO1) + if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) vout->win.global_alpha = 255; else vout->win.global_alpha = f->fmt.win.global_alpha; @@ -1788,7 +1792,9 @@ static int vidioc_s_fbuf(struct file *file, void *fh, if (ovl->manager && ovl->manager->get_manager_info && ovl->manager->set_manager_info) { ovl->manager->get_manager_info(ovl->manager, &info); - info.alpha_enabled = enable; + /* enable this only if there is no zorder cap */ + if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) + info.partial_alpha_enabled = enable; if (ovl->manager->set_manager_info(ovl->manager, &info)) return -EINVAL; } @@ -1820,7 +1826,7 @@ static int vidioc_g_fbuf(struct file *file, void *fh, } if (ovl->manager && ovl->manager->get_manager_info) { ovl->manager->get_manager_info(ovl->manager, &info); - if (info.alpha_enabled) + if (info.partial_alpha_enabled) a->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA; } diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 5e6849e..e0639d3 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -179,7 +179,8 @@ static void dispc_save_context(void) SR(CONTROL); SR(CONFIG); SR(LINE_NUMBER); - if (dss_has_feature(FEAT_GLOBAL_ALPHA)) + if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) SR(GLOBAL_ALPHA); if (dss_has_feature(FEAT_MGR_LCD2)) { SR(CONTROL2); @@ -293,7 +294,8 @@ static void dispc_restore_context(void) /*RR(CONTROL);*/ RR(CONFIG); RR(LINE_NUMBER); - if (dss_has_feature(FEAT_GLOBAL_ALPHA)) + if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) RR(GLOBAL_ALPHA); if (dss_has_feature(FEAT_MGR_LCD2)) RR(CONFIG2); @@ -2159,38 +2161,35 @@ void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) else /* OMAP_DSS_CHANNEL_LCD2 */ REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10); } -void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable) + +void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable) { - if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) + if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) return; if (ch == OMAP_DSS_CHANNEL_LCD) REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); else if (ch == OMAP_DSS_CHANNEL_DIGIT) REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); - else /* OMAP_DSS_CHANNEL_LCD2 */ - REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18); } -bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch) + +bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch) { bool enabled; - if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) + if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) return false; if (ch == OMAP_DSS_CHANNEL_LCD) enabled = REG_GET(DISPC_CONFIG, 18, 18); else if (ch == OMAP_DSS_CHANNEL_DIGIT) enabled = REG_GET(DISPC_CONFIG, 19, 19); - else if (ch == OMAP_DSS_CHANNEL_LCD2) - enabled = REG_GET(DISPC_CONFIG2, 18, 18); else BUG(); return enabled; } - bool dispc_mgr_trans_key_enabled(enum omap_channel ch) { bool enabled; @@ -2603,7 +2602,8 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_CAPABLE); DUMPREG(DISPC_LINE_STATUS); DUMPREG(DISPC_LINE_NUMBER); - if (dss_has_feature(FEAT_GLOBAL_ALPHA)) + if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || + dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) DUMPREG(DISPC_GLOBAL_ALPHA); if (dss_has_feature(FEAT_MGR_LCD2)) { DUMPREG(DISPC_CONTROL2); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 47eebd8..a37aef2 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -430,9 +430,9 @@ void dispc_mgr_get_trans_key(enum omap_channel ch, enum omap_dss_trans_key_type *type, u32 *trans_key); void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable); -void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable); +void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable); bool dispc_mgr_trans_key_enabled(enum omap_channel ch); -bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch); +bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch); void dispc_mgr_set_lcd_timings(enum omap_channel channel, struct omap_video_timings *timings); void dispc_mgr_set_pol_freq(enum omap_channel channel, diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 47e66d8..70d5b9e 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -248,15 +248,16 @@ static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = { static const enum omap_overlay_caps omap4_dss_overlay_caps[] = { /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA, + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | + OMAP_DSS_OVL_CAP_ZORDER, /* OMAP_DSS_VIDEO1 */ OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA, + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER, /* OMAP_DSS_VIDEO2 */ OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA, + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER, }; static const char * const omap2_dss_clk_source_names[] = { @@ -342,13 +343,13 @@ static const struct omap_dss_features omap3430_dss_features = { .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | + FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF | FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC | FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD | - FEAT_FIR_COEF_V, + FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER, .num_mgrs = 2, .num_ovls = 3, @@ -366,13 +367,13 @@ static const struct omap_dss_features omap3630_dss_features = { .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | + FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG | FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD | - FEAT_FIR_COEF_V, + FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER, .num_mgrs = 2, .num_ovls = 3, @@ -392,12 +393,12 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_MGR_LCD2 | FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC | FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH | FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | - FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V, + FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V | + FEAT_ALPHA_FREE_ZORDER, .num_mgrs = 3, .num_ovls = 3, @@ -416,13 +417,12 @@ static const struct omap_dss_features omap4_dss_features = { .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_MGR_LCD2 | FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC | FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH | FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR | - FEAT_PRELOAD | FEAT_FIR_COEF_V, + FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER, .num_mgrs = 3, .num_ovls = 3, diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index cd60644..e81271a 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -31,7 +31,6 @@ /* DSS has feature id */ enum dss_feat_id { - FEAT_GLOBAL_ALPHA = 1 << 0, FEAT_LCDENABLEPOL = 1 << 3, FEAT_LCDENABLESIGNAL = 1 << 4, FEAT_PCKFREEENABLE = 1 << 5, @@ -57,6 +56,8 @@ enum dss_feat_id { FEAT_CPR = 1 << 23, FEAT_PRELOAD = 1 << 24, FEAT_FIR_COEF_V = 1 << 25, + FEAT_ALPHA_FIXED_ZORDER = 1 << 26, + FEAT_ALPHA_FREE_ZORDER = 1 << 27, }; /* DSS register field id */ diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index fdbbeeb..6e63845 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -249,7 +249,10 @@ static ssize_t manager_trans_key_enabled_store(struct omap_overlay_manager *mgr, static ssize_t manager_alpha_blending_enabled_show( struct omap_overlay_manager *mgr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.alpha_enabled); + WARN_ON(!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)); + + return snprintf(buf, PAGE_SIZE, "%d\n", + mgr->info.partial_alpha_enabled); } static ssize_t manager_alpha_blending_enabled_store( @@ -260,13 +263,15 @@ static ssize_t manager_alpha_blending_enabled_store( bool enable; int r; + WARN_ON(!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)); + r = strtobool(buf, &enable); if (r) return r; mgr->get_manager_info(mgr, &info); - info.alpha_enabled = enable; + info.partial_alpha_enabled = enable; r = mgr->set_manager_info(mgr, &info); if (r) @@ -966,7 +971,7 @@ static void configure_manager(enum omap_channel channel) dispc_mgr_set_default_color(channel, mi->default_color); dispc_mgr_set_trans_key(channel, mi->trans_key_type, mi->trans_key); dispc_mgr_enable_trans_key(channel, mi->trans_enabled); - dispc_mgr_enable_alpha_blending(channel, mi->alpha_enabled); + dispc_mgr_enable_alpha_fixed_zorder(channel, mi->partial_alpha_enabled); if (dss_has_feature(FEAT_CPR)) { dispc_mgr_enable_cpr(channel, mi->cpr_enable); dispc_mgr_set_cpr_coef(channel, &mi->cpr_coefs); @@ -1481,12 +1486,17 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) static int dss_check_manager(struct omap_overlay_manager *mgr) { - /* OMAP supports only graphics source transparency color key and alpha - * blending simultaneously. See TRM 15.4.2.4.2.2 Alpha Mode */ - - if (mgr->info.alpha_enabled && mgr->info.trans_enabled && - mgr->info.trans_key_type != OMAP_DSS_COLOR_KEY_GFX_DST) - return -EINVAL; + if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) { + /* + * OMAP3 supports only graphics source transparency color key + * and alpha blending simultaneously. See TRM 15.4.2.4.2.2 + * Alpha Mode + */ + if (mgr->info.partial_alpha_enabled && mgr->info.trans_enabled + && mgr->info.trans_key_type != + OMAP_DSS_COLOR_KEY_GFX_DST) + return -EINVAL; + } return 0; } diff --git a/include/video/omapdss.h b/include/video/omapdss.h index c62b9a4..5f0ce5e 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -179,6 +179,7 @@ enum omap_overlay_caps { OMAP_DSS_OVL_CAP_SCALE = 1 << 0, OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, + OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, }; enum omap_overlay_manager_caps { @@ -406,7 +407,7 @@ struct omap_overlay_manager_info { u32 trans_key; bool trans_enabled; - bool alpha_enabled; + bool partial_alpha_enabled; bool cpr_enable; struct omap_dss_cpr_coefs cpr_coefs;