From patchwork Wed Jan 13 23:27:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: m-karicheri2@ti.com X-Patchwork-Id: 2452 Return-path: Envelope-to: mchehab@infradead.org Delivery-date: Wed, 13 Jan 2010 23:27:22 +0000 Received: from bombadil.infradead.org [18.85.46.34] by pedra with IMAP (fetchmail-6.3.6) for (single-drop); Wed, 13 Jan 2010 21:27:49 -0200 (BRST) Received: from vger.kernel.org ([209.132.180.67]) by bombadil.infradead.org with esmtp (Exim 4.69 #1 (Red Hat Linux)) id 1NVCcU-0000Iy-6b; Wed, 13 Jan 2010 23:27:22 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753875Ab0AMX1U (ORCPT + 1 other); Wed, 13 Jan 2010 18:27:20 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753826Ab0AMX1T (ORCPT ); Wed, 13 Jan 2010 18:27:19 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:60738 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751713Ab0AMX1S (ORCPT ); Wed, 13 Jan 2010 18:27:18 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o0DNRBa6025319 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 13 Jan 2010 17:27:11 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o0DNRBWx003310; Wed, 13 Jan 2010 17:27:11 -0600 (CST) Received: from gt516km11.gt.design.ti.com (gt516km11.gt.design.ti.com [158.218.100.179]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o0DNRAZ03103; Wed, 13 Jan 2010 17:27:10 -0600 (CST) Received: from gt516km11.gt.design.ti.com (localhost.localdomain [127.0.0.1]) by gt516km11.gt.design.ti.com (8.13.1/8.13.1) with ESMTP id o0DNRAVG014667; Wed, 13 Jan 2010 18:27:10 -0500 Received: (from a0868495@localhost) by gt516km11.gt.design.ti.com (8.13.1/8.13.1/Submit) id o0DNRAMY014664; Wed, 13 Jan 2010 18:27:10 -0500 From: m-karicheri2@ti.com To: linux-media@vger.kernel.org, hverkuil@xs4all.nl, khilman@deeprootsystems.com, mchehab@infradead.org Cc: davinci-linux-open-source@linux.davincidsp.com, Muralidharan Karicheri Subject: [PATCH - v4 4/4] DaVinci vpfe-capture - converting ccdc drivers to platform-drivers Date: Wed, 13 Jan 2010 18:27:08 -0500 Message-Id: <1263425228-14625-4-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1263425228-14625-3-git-send-email-m-karicheri2@ti.com> References: <1263425228-14625-1-git-send-email-m-karicheri2@ti.com> <1263425228-14625-2-git-send-email-m-karicheri2@ti.com> <1263425228-14625-3-git-send-email-m-karicheri2@ti.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Muralidharan Karicheri This adds platform code for ccdc driver on DM355 and DM6446. Following changes are made as part of this patch:- 1) new ccdc platform devices added 2) added clock aliases master and slave for CCDC clocks 3) added dm355_ccdc_setup_pinmux() pin-mux setup hook in dm355 ccdc driver platform data Reviewed-by: Vaibhav Hiremath Reviewed-by: Kevin Hilman Reviewed-by: Hans Verkuil Signed-off-by: Muralidharan Karicheri --- Re-sending the patches based on Kevin's comments. Following are the changes from v3 :- - added ccdc clocks through clk_add_alias() calls This combines the two patches sent earlier to change the clock configuration and converting ccdc drivers to platform drivers. This has updated comments against v2 of these patches. Two new clocks "master" and "slave" are defined for ccdc driver as per comments from Kevin Hilman. Applies to Linus tree arch/arm/mach-davinci/dm355.c | 43 +++++++++++++++++++++++++++------------ arch/arm/mach-davinci/dm644x.c | 21 ++++++++++++++++++- 2 files changed, 50 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index dedf4d4..d84e854 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -125,7 +125,6 @@ static struct clk vpss_slave_clk = { .lpsc = DAVINCI_LPSC_VPSSSLV, }; - static struct clk clkout1_clk = { .name = "clkout1", .parent = &pll1_aux_clk, @@ -665,6 +664,17 @@ static struct platform_device dm355_asp1_device = { .resource = dm355_asp1_resources, }; +static void dm355_ccdc_setup_pinmux(void) +{ + davinci_cfg_reg(DM355_VIN_PCLK); + davinci_cfg_reg(DM355_VIN_CAM_WEN); + davinci_cfg_reg(DM355_VIN_CAM_VD); + davinci_cfg_reg(DM355_VIN_CAM_HD); + davinci_cfg_reg(DM355_VIN_YIN_EN); + davinci_cfg_reg(DM355_VIN_CINL_EN); + davinci_cfg_reg(DM355_VIN_CINH_EN); +} + static struct resource dm355_vpss_resources[] = { { /* VPSS BL Base address */ @@ -701,6 +711,10 @@ static struct resource vpfe_resources[] = { .end = IRQ_VDINT1, .flags = IORESOURCE_IRQ, }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct resource dm355_ccdc_resource[] = { /* CCDC Base address */ { .flags = IORESOURCE_MEM, @@ -708,8 +722,18 @@ static struct resource vpfe_resources[] = { .end = 0x01c70600 + 0x1ff, }, }; +static struct platform_device dm355_ccdc_dev = { + .name = "dm355_ccdc", + .id = -1, + .num_resources = ARRAY_SIZE(dm355_ccdc_resource), + .resource = dm355_ccdc_resource, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = dm355_ccdc_setup_pinmux, + }, +}; -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); static struct platform_device vpfe_capture_dev = { .name = CAPTURE_DRV_NAME, .id = -1, @@ -857,20 +881,13 @@ static int __init dm355_init_devices(void) if (!cpu_is_davinci_dm355()) return 0; + /* Add ccdc clock aliases */ + clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL); + clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL); davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); platform_device_register(&dm355_vpss_device); - /* - * setup Mux configuration for vpfe input and register - * vpfe capture platform device - */ - davinci_cfg_reg(DM355_VIN_PCLK); - davinci_cfg_reg(DM355_VIN_CAM_WEN); - davinci_cfg_reg(DM355_VIN_CAM_VD); - davinci_cfg_reg(DM355_VIN_CAM_HD); - davinci_cfg_reg(DM355_VIN_YIN_EN); - davinci_cfg_reg(DM355_VIN_CINL_EN); - davinci_cfg_reg(DM355_VIN_CINH_EN); + platform_device_register(&dm355_ccdc_dev); platform_device_register(&vpfe_capture_dev); return 0; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 2cd0081..92aeb56 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -612,6 +612,11 @@ static struct resource vpfe_resources[] = { .end = IRQ_VDINT1, .flags = IORESOURCE_IRQ, }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct resource dm644x_ccdc_resource[] = { + /* CCDC Base address */ { .start = 0x01c70400, .end = 0x01c70400 + 0xff, @@ -619,7 +624,17 @@ static struct resource vpfe_resources[] = { }, }; -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct platform_device dm644x_ccdc_dev = { + .name = "dm644x_ccdc", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), + .resource = dm644x_ccdc_resource, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + static struct platform_device vpfe_capture_dev = { .name = CAPTURE_DRV_NAME, .id = -1, @@ -769,9 +784,13 @@ static int __init dm644x_init_devices(void) if (!cpu_is_davinci_dm644x()) return 0; + /* Add ccdc clock aliases */ + clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); + clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); platform_device_register(&dm644x_edma_device); platform_device_register(&dm644x_emac_device); platform_device_register(&dm644x_vpss_device); + platform_device_register(&dm644x_ccdc_dev); platform_device_register(&vpfe_capture_dev); return 0;