LinuxTV Patchwork [v1,1/3] dt-bindings: Document MIPID02 bindings

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Submitter Mickael Guene
Date March 12, 2019, 6:44 a.m.
Message ID <1552373045-134493-2-git-send-email-mickael.guene@st.com>
Download mbox | patch
Permalink /patch/55000/
State New
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Comments

Mickael Guene - March 12, 2019, 6:44 a.m.
This adds documentation of device tree for MIPID02 CSI-2 to PARALLEL
bridge.

Signed-off-by: Mickael Guene <mickael.guene@st.com>
---

 .../bindings/media/i2c/st,st-mipid02.txt           | 69 ++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
Sakari Ailus - March 16, 2019, 9:46 p.m.
Hi Mickael,

Thanks for the patchset.

On Tue, Mar 12, 2019 at 07:44:03AM +0100, Mickael Guene wrote:
> This adds documentation of device tree for MIPID02 CSI-2 to PARALLEL
> bridge.
> 
> Signed-off-by: Mickael Guene <mickael.guene@st.com>
> ---
> 
>  .../bindings/media/i2c/st,st-mipid02.txt           | 69 ++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> new file mode 100644
> index 0000000..a1855da
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> @@ -0,0 +1,69 @@
> +STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
> +
> +MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
> +time. Active port input stream will be de-serialized and its content outputted
> +through PARALLEL output port.
> +CSI-2 first input port is a dual lane 800Mbps whereas CSI-2 second input port is

800 Mbps per lane (or total)?

> +a single lane 800Mbps. Both ports support clock and data lane polarity swap.
> +First port also supports data lane swap.
> +PARALLEL output port has a maximum width of 12 bits.
> +Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
> +YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
> +
> +Required Properties:
> +- compatible: should be "st,st-mipid02"
> +- clocks: reference to the xclk input clock.
> +- clock-names: should be "xclk".
> +- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
> +- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.

Perhaps Rob can confirm, but AFAIR the custom is to use lower case letters.

> +
> +Optional Properties:
> +- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
> +	       This is an active low signal to the mipid02.
> +
> +Required subnodes:
> +  - ports: A ports node with one port child node per device input and output
> +	   port, in accordance with the video interface bindings defined in
> +	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +	   port nodes are numbered as follows:
> +
> +	   Port Description
> +	   -----------------------------
> +	   0    CSI-2 first input port
> +	   1    CSI-2 second input port
> +	   2    PARALLEL output

Please document which endpoint properties are relevant. From the above
description I'd presume this to be at least clock-lanes (1st input),
data-lanes, lane-polarities (for CSI-2) as well as bus-width for the
parallel bus.

> +
> +Example:
> +
> +mipid02: mipid02@14 {

The node should be a generic name. "csi2rx" is used by a few devices now.

> +	compatible = "st,st-mipid02";
> +	reg = <0x14>;
> +	status = "okay";
> +	clocks = <&clk_ext_camera_12>;
> +	clock-names = "xclk";
> +	VDDE-supply = <&vdd>;
> +	VDDIN-supply = <&vdd>;
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		port@0 {
> +			reg = <0>;
> +
> +			ep0: endpoint {
> +				clock-lanes = <0>;
> +				data-lanes = <1 2>;
> +				remote-endpoint = <&mipi_csi2_in>;
> +			};
> +		};
> +		port@2 {
> +			reg = <2>;
> +
> +			ep2: endpoint {
> +				bus-width = <8>;
> +				hsync-active = <0>;
> +				vsync-active = <0>;
> +				remote-endpoint = <&parallel_out>;
> +			};
> +		};
> +	};
> +};
Mickael Guene - March 18, 2019, 8:28 a.m.
Hi Sakari,

Thanks for your review. Find my comments below.

On 3/16/19 22:46, Sakari Ailus wrote:
> Hi Mickael,
> 
> Thanks for the patchset.
> 
> On Tue, Mar 12, 2019 at 07:44:03AM +0100, Mickael Guene wrote:
>> This adds documentation of device tree for MIPID02 CSI-2 to PARALLEL
>> bridge.
>>
>> Signed-off-by: Mickael Guene <mickael.guene@st.com>
>> ---
>>
>>  .../bindings/media/i2c/st,st-mipid02.txt           | 69 ++++++++++++++++++++++
>>  1 file changed, 69 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
>> new file mode 100644
>> index 0000000..a1855da
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
>> @@ -0,0 +1,69 @@
>> +STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
>> +
>> +MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
>> +time. Active port input stream will be de-serialized and its content outputted
>> +through PARALLEL output port.
>> +CSI-2 first input port is a dual lane 800Mbps whereas CSI-2 second input port is
> 
> 800 Mbps per lane (or total)?
> 
800 Mbps per lane. I will document it.
>> +a single lane 800Mbps. Both ports support clock and data lane polarity swap.
>> +First port also supports data lane swap.
>> +PARALLEL output port has a maximum width of 12 bits.
>> +Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
>> +YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
>> +
>> +Required Properties:
>> +- compatible: should be "st,st-mipid02"
>> +- clocks: reference to the xclk input clock.
>> +- clock-names: should be "xclk".
>> +- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
>> +- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
> 
> Perhaps Rob can confirm, but AFAIR the custom is to use lower case letters.
> 
 It seems there is a 50-50 ratio between upper and lower case usage in
Documentation/devicetree/bindings/media/i2. I will wait Rob's answer to change
it or not.
>> +
>> +Optional Properties:
>> +- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
>> +	       This is an active low signal to the mipid02.
>> +
>> +Required subnodes:
>> +  - ports: A ports node with one port child node per device input and output
>> +	   port, in accordance with the video interface bindings defined in
>> +	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
>> +	   port nodes are numbered as follows:
>> +
>> +	   Port Description
>> +	   -----------------------------
>> +	   0    CSI-2 first input port
>> +	   1    CSI-2 second input port
>> +	   2    PARALLEL output
> 
> Please document which endpoint properties are relevant. From the above
> description I'd presume this to be at least clock-lanes (1st input),
> data-lanes, lane-polarities (for CSI-2) as well as bus-width for the
> parallel bus.
> 
ok. I will add documentation.
>> +
>> +Example:
>> +
>> +mipid02: mipid02@14 {
> 
> The node should be a generic name. "csi2rx" is used by a few devices now.
>
 If I understand you well, you would prefer:
csi2rx: mipid02@14 {
 I show no usage of csi2rx node naming except for MIPI-CSI2 RX controller.
>> +	compatible = "st,st-mipid02";
>> +	reg = <0x14>;
>> +	status = "okay";
>> +	clocks = <&clk_ext_camera_12>;
>> +	clock-names = "xclk";
>> +	VDDE-supply = <&vdd>;
>> +	VDDIN-supply = <&vdd>;
>> +	ports {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		port@0 {
>> +			reg = <0>;
>> +
>> +			ep0: endpoint {
>> +				clock-lanes = <0>;
>> +				data-lanes = <1 2>;
>> +				remote-endpoint = <&mipi_csi2_in>;
>> +			};
>> +		};
>> +		port@2 {
>> +			reg = <2>;
>> +
>> +			ep2: endpoint {
>> +				bus-width = <8>;
>> +				hsync-active = <0>;
>> +				vsync-active = <0>;
>> +				remote-endpoint = <&parallel_out>;
>> +			};
>> +		};
>> +	};
>> +};
>
Sakari Ailus - March 18, 2019, 8:48 a.m.
On Mon, Mar 18, 2019 at 08:28:36AM +0000, Mickael GUENE wrote:
> Hi Sakari,
> 
> Thanks for your review. Find my comments below.
> 
> On 3/16/19 22:46, Sakari Ailus wrote:
> > Hi Mickael,
> > 
> > Thanks for the patchset.
> > 
> > On Tue, Mar 12, 2019 at 07:44:03AM +0100, Mickael Guene wrote:
> >> This adds documentation of device tree for MIPID02 CSI-2 to PARALLEL
> >> bridge.
> >>
> >> Signed-off-by: Mickael Guene <mickael.guene@st.com>
> >> ---
> >>
> >>  .../bindings/media/i2c/st,st-mipid02.txt           | 69 ++++++++++++++++++++++
> >>  1 file changed, 69 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> >> new file mode 100644
> >> index 0000000..a1855da
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
> >> @@ -0,0 +1,69 @@
> >> +STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
> >> +
> >> +MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
> >> +time. Active port input stream will be de-serialized and its content outputted
> >> +through PARALLEL output port.
> >> +CSI-2 first input port is a dual lane 800Mbps whereas CSI-2 second input port is
> > 
> > 800 Mbps per lane (or total)?
> > 
> 800 Mbps per lane. I will document it.
> >> +a single lane 800Mbps. Both ports support clock and data lane polarity swap.
> >> +First port also supports data lane swap.
> >> +PARALLEL output port has a maximum width of 12 bits.
> >> +Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
> >> +YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
> >> +
> >> +Required Properties:
> >> +- compatible: should be "st,st-mipid02"
> >> +- clocks: reference to the xclk input clock.
> >> +- clock-names: should be "xclk".
> >> +- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
> >> +- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
> > 
> > Perhaps Rob can confirm, but AFAIR the custom is to use lower case letters.
> > 
>  It seems there is a 50-50 ratio between upper and lower case usage in
> Documentation/devicetree/bindings/media/i2. I will wait Rob's answer to change
> it or not.
> >> +
> >> +Optional Properties:
> >> +- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
> >> +	       This is an active low signal to the mipid02.
> >> +
> >> +Required subnodes:
> >> +  - ports: A ports node with one port child node per device input and output
> >> +	   port, in accordance with the video interface bindings defined in
> >> +	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
> >> +	   port nodes are numbered as follows:
> >> +
> >> +	   Port Description
> >> +	   -----------------------------
> >> +	   0    CSI-2 first input port
> >> +	   1    CSI-2 second input port
> >> +	   2    PARALLEL output
> > 
> > Please document which endpoint properties are relevant. From the above
> > description I'd presume this to be at least clock-lanes (1st input),
> > data-lanes, lane-polarities (for CSI-2) as well as bus-width for the
> > parallel bus.
> > 
> ok. I will add documentation.
> >> +
> >> +Example:
> >> +
> >> +mipid02: mipid02@14 {
> > 
> > The node should be a generic name. "csi2rx" is used by a few devices now.
> >
>  If I understand you well, you would prefer:
> csi2rx: mipid02@14 {
>  I show no usage of csi2rx node naming except for MIPI-CSI2 RX controller.

The other way around. :)

The label can be more or less anything AFAIK.
Mickael Guene - March 18, 2019, 9:08 a.m.
Sakari,

>>>> +
>>>> +Example:
>>>> +
>>>> +mipid02: mipid02@14 {
>>>
>>> The node should be a generic name. "csi2rx" is used by a few devices now.
>>>
>>  If I understand you well, you would prefer:
>> csi2rx: mipid02@14 {
>>  I show no usage of csi2rx node naming except for MIPI-CSI2 RX controller.
> 
> The other way around. :)
> 
> The label can be more or less anything AFAIK.
> 
 Ok got it !!! So something like 'mipid02: bridge@14 {' should be ok ?

Thx

Patch

diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
new file mode 100644
index 0000000..a1855da
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt
@@ -0,0 +1,69 @@ 
+STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
+
+MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
+time. Active port input stream will be de-serialized and its content outputted
+through PARALLEL output port.
+CSI-2 first input port is a dual lane 800Mbps whereas CSI-2 second input port is
+a single lane 800Mbps. Both ports support clock and data lane polarity swap.
+First port also supports data lane swap.
+PARALLEL output port has a maximum width of 12 bits.
+Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
+YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
+
+Required Properties:
+- compatible: should be "st,st-mipid02"
+- clocks: reference to the xclk input clock.
+- clock-names: should be "xclk".
+- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
+- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
+	       This is an active low signal to the mipid02.
+
+Required subnodes:
+  - ports: A ports node with one port child node per device input and output
+	   port, in accordance with the video interface bindings defined in
+	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
+	   port nodes are numbered as follows:
+
+	   Port Description
+	   -----------------------------
+	   0    CSI-2 first input port
+	   1    CSI-2 second input port
+	   2    PARALLEL output
+
+Example:
+
+mipid02: mipid02@14 {
+	compatible = "st,st-mipid02";
+	reg = <0x14>;
+	status = "okay";
+	clocks = <&clk_ext_camera_12>;
+	clock-names = "xclk";
+	VDDE-supply = <&vdd>;
+	VDDIN-supply = <&vdd>;
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+
+			ep0: endpoint {
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&mipi_csi2_in>;
+			};
+		};
+		port@2 {
+			reg = <2>;
+
+			ep2: endpoint {
+				bus-width = <8>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				remote-endpoint = <&parallel_out>;
+			};
+		};
+	};
+};

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