diff mbox series

hantro: Fix RK3399 H.264 format advertising

Message ID 20220629195624.45745-1-ezequiel@vanguardiasur.com.ar (mailing list archive)
State Accepted
Delegated to: Hans Verkuil
Headers
Series hantro: Fix RK3399 H.264 format advertising |

Commit Message

Ezequiel Garcia June 29, 2022, 7:56 p.m. UTC 
Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect
of exposing H.264 coded format as supported on RK3399.

Fix this and clarify how the codec is explicitly disabled on RK399 on
this driver.

Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
---
 .../staging/media/hantro/rockchip_vpu_hw.c    | 60 ++++++++++++++++---
 1 file changed, 53 insertions(+), 7 deletions(-)

Comments

Nicolas Dufresne June 29, 2022, 8:07 p.m. UTC | #1 
Hi Ezequiel,

Le mercredi 29 juin 2022 à 16:56 -0300, Ezequiel Garcia a écrit :
> Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect
> of exposing H.264 coded format as supported on RK3399.
> 
> Fix this and clarify how the codec is explicitly disabled on RK399 on

RK399 -> RK3399

> this driver.
> 
> Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Thanks for fixing this. The bogus format (without associated controls) is not
gone. With the right video node value:

  v4l2-ctl -D -dN --list-formats-out

Tested-By: Nicolas Dufresne <nicolas.dufresne@collabora.com>

> ---
>  .../staging/media/hantro/rockchip_vpu_hw.c    | 60 ++++++++++++++++---
>  1 file changed, 53 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> index 098486b9ec27..26e16b5a6a70 100644
> --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
> +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> @@ -182,7 +182,7 @@ static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
>  	},
>  };
>  
> -static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> +static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
>  	{
>  		.fourcc = V4L2_PIX_FMT_NV12,
>  		.codec_mode = HANTRO_MODE_NONE,
> @@ -236,6 +236,47 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
>  	},
>  };
>  
> +static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> +	{
> +		.fourcc = V4L2_PIX_FMT_NV12,
> +		.codec_mode = HANTRO_MODE_NONE,
> +		.frmsize = {
> +			.min_width = FMT_MIN_WIDTH,
> +			.max_width = FMT_FHD_WIDTH,
> +			.step_width = MB_DIM,
> +			.min_height = FMT_MIN_HEIGHT,
> +			.max_height = FMT_FHD_HEIGHT,
> +			.step_height = MB_DIM,
> +		},
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
> +		.codec_mode = HANTRO_MODE_MPEG2_DEC,
> +		.max_depth = 2,
> +		.frmsize = {
> +			.min_width = FMT_MIN_WIDTH,
> +			.max_width = FMT_FHD_WIDTH,
> +			.step_width = MB_DIM,
> +			.min_height = FMT_MIN_HEIGHT,
> +			.max_height = FMT_FHD_HEIGHT,
> +			.step_height = MB_DIM,
> +		},
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
> +		.codec_mode = HANTRO_MODE_VP8_DEC,
> +		.max_depth = 2,
> +		.frmsize = {
> +			.min_width = FMT_MIN_WIDTH,
> +			.max_width = FMT_UHD_WIDTH,
> +			.step_width = MB_DIM,
> +			.min_height = FMT_MIN_HEIGHT,
> +			.max_height = FMT_UHD_HEIGHT,
> +			.step_height = MB_DIM,
> +		},
> +	},
> +};
> +
>  static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
>  {
>  	struct hantro_dev *vpu = dev_id;
> @@ -548,8 +589,8 @@ const struct hantro_variant rk3288_vpu_variant = {
>  
>  const struct hantro_variant rk3328_vpu_variant = {
>  	.dec_offset = 0x400,
> -	.dec_fmts = rk3399_vpu_dec_fmts,
> -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
>  		 HANTRO_H264_DECODER,
>  	.codec_ops = rk3399_vpu_codec_ops,
> @@ -560,6 +601,11 @@ const struct hantro_variant rk3328_vpu_variant = {
>  	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
>  };
>  
> +/*
> + * H.264 decoding explicitly disabled in RK3399.
> + * This ensures userspace applications use the Rockchip VDEC core,
> + * which has better performance.
> + */
>  const struct hantro_variant rk3399_vpu_variant = {
>  	.enc_offset = 0x0,
>  	.enc_fmts = rockchip_vpu_enc_fmts,
> @@ -579,8 +625,8 @@ const struct hantro_variant rk3399_vpu_variant = {
>  
>  const struct hantro_variant rk3568_vpu_variant = {
>  	.dec_offset = 0x400,
> -	.dec_fmts = rk3399_vpu_dec_fmts,
> -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec = HANTRO_MPEG2_DECODER |
>  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
>  	.codec_ops = rk3399_vpu_codec_ops,
> @@ -596,8 +642,8 @@ const struct hantro_variant px30_vpu_variant = {
>  	.enc_fmts = rockchip_vpu_enc_fmts,
>  	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
>  	.dec_offset = 0x400,
> -	.dec_fmts = rk3399_vpu_dec_fmts,
> -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
>  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
>  	.codec_ops = rk3399_vpu_codec_ops,

And code looks good (just found a small commit message typo).

Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>

regards,
Nicolas
Nicolas Dufresne July 4, 2022, 4:09 p.m. UTC | #2 
Le mercredi 29 juin 2022 à 16:07 -0400, Nicolas Dufresne a écrit :
> Hi Ezequiel,
> 
> Le mercredi 29 juin 2022 à 16:56 -0300, Ezequiel Garcia a écrit :
> > Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> > enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect
> > of exposing H.264 coded format as supported on RK3399.
> > 
> > Fix this and clarify how the codec is explicitly disabled on RK399 on
> 
> RK399 -> RK3399
> 
> > this driver.
> > 
> > Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> > Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 
> Thanks for fixing this. The bogus format (without associated controls) is not

Sorry:
* is now

> gone. With the right video node value:
> 
>   v4l2-ctl -D -dN --list-formats-out
> 
> Tested-By: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> 
> > ---
> >  .../staging/media/hantro/rockchip_vpu_hw.c    | 60 ++++++++++++++++---
> >  1 file changed, 53 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> > index 098486b9ec27..26e16b5a6a70 100644
> > --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
> > +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> > @@ -182,7 +182,7 @@ static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
> >  	},
> >  };
> >  
> > -static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> > +static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
> >  	{
> >  		.fourcc = V4L2_PIX_FMT_NV12,
> >  		.codec_mode = HANTRO_MODE_NONE,
> > @@ -236,6 +236,47 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> >  	},
> >  };
> >  
> > +static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> > +	{
> > +		.fourcc = V4L2_PIX_FMT_NV12,
> > +		.codec_mode = HANTRO_MODE_NONE,
> > +		.frmsize = {
> > +			.min_width = FMT_MIN_WIDTH,
> > +			.max_width = FMT_FHD_WIDTH,
> > +			.step_width = MB_DIM,
> > +			.min_height = FMT_MIN_HEIGHT,
> > +			.max_height = FMT_FHD_HEIGHT,
> > +			.step_height = MB_DIM,
> > +		},
> > +	},
> > +	{
> > +		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
> > +		.codec_mode = HANTRO_MODE_MPEG2_DEC,
> > +		.max_depth = 2,
> > +		.frmsize = {
> > +			.min_width = FMT_MIN_WIDTH,
> > +			.max_width = FMT_FHD_WIDTH,
> > +			.step_width = MB_DIM,
> > +			.min_height = FMT_MIN_HEIGHT,
> > +			.max_height = FMT_FHD_HEIGHT,
> > +			.step_height = MB_DIM,
> > +		},
> > +	},
> > +	{
> > +		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
> > +		.codec_mode = HANTRO_MODE_VP8_DEC,
> > +		.max_depth = 2,
> > +		.frmsize = {
> > +			.min_width = FMT_MIN_WIDTH,
> > +			.max_width = FMT_UHD_WIDTH,
> > +			.step_width = MB_DIM,
> > +			.min_height = FMT_MIN_HEIGHT,
> > +			.max_height = FMT_UHD_HEIGHT,
> > +			.step_height = MB_DIM,
> > +		},
> > +	},
> > +};
> > +
> >  static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
> >  {
> >  	struct hantro_dev *vpu = dev_id;
> > @@ -548,8 +589,8 @@ const struct hantro_variant rk3288_vpu_variant = {
> >  
> >  const struct hantro_variant rk3328_vpu_variant = {
> >  	.dec_offset = 0x400,
> > -	.dec_fmts = rk3399_vpu_dec_fmts,
> > -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> > +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> > +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
> >  	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
> >  		 HANTRO_H264_DECODER,
> >  	.codec_ops = rk3399_vpu_codec_ops,
> > @@ -560,6 +601,11 @@ const struct hantro_variant rk3328_vpu_variant = {
> >  	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
> >  };
> >  
> > +/*
> > + * H.264 decoding explicitly disabled in RK3399.
> > + * This ensures userspace applications use the Rockchip VDEC core,
> > + * which has better performance.
> > + */
> >  const struct hantro_variant rk3399_vpu_variant = {
> >  	.enc_offset = 0x0,
> >  	.enc_fmts = rockchip_vpu_enc_fmts,
> > @@ -579,8 +625,8 @@ const struct hantro_variant rk3399_vpu_variant = {
> >  
> >  const struct hantro_variant rk3568_vpu_variant = {
> >  	.dec_offset = 0x400,
> > -	.dec_fmts = rk3399_vpu_dec_fmts,
> > -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> > +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> > +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
> >  	.codec = HANTRO_MPEG2_DECODER |
> >  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
> >  	.codec_ops = rk3399_vpu_codec_ops,
> > @@ -596,8 +642,8 @@ const struct hantro_variant px30_vpu_variant = {
> >  	.enc_fmts = rockchip_vpu_enc_fmts,
> >  	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
> >  	.dec_offset = 0x400,
> > -	.dec_fmts = rk3399_vpu_dec_fmts,
> > -	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> > +	.dec_fmts = rockchip_vdpu2_dec_fmts,
> > +	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
> >  	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
> >  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
> >  	.codec_ops = rk3399_vpu_codec_ops,
> 
> And code looks good (just found a small commit message typo).
> 
> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> 
> regards,
> Nicolas
> 
>
diff mbox series

Patch

diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
index 098486b9ec27..26e16b5a6a70 100644
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
@@ -182,7 +182,7 @@  static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
 	},
 };
 
-static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
+static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
 	{
 		.fourcc = V4L2_PIX_FMT_NV12,
 		.codec_mode = HANTRO_MODE_NONE,
@@ -236,6 +236,47 @@  static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
 	},
 };
 
+static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
+	{
+		.fourcc = V4L2_PIX_FMT_NV12,
+		.codec_mode = HANTRO_MODE_NONE,
+		.frmsize = {
+			.min_width = FMT_MIN_WIDTH,
+			.max_width = FMT_FHD_WIDTH,
+			.step_width = MB_DIM,
+			.min_height = FMT_MIN_HEIGHT,
+			.max_height = FMT_FHD_HEIGHT,
+			.step_height = MB_DIM,
+		},
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
+		.codec_mode = HANTRO_MODE_MPEG2_DEC,
+		.max_depth = 2,
+		.frmsize = {
+			.min_width = FMT_MIN_WIDTH,
+			.max_width = FMT_FHD_WIDTH,
+			.step_width = MB_DIM,
+			.min_height = FMT_MIN_HEIGHT,
+			.max_height = FMT_FHD_HEIGHT,
+			.step_height = MB_DIM,
+		},
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
+		.codec_mode = HANTRO_MODE_VP8_DEC,
+		.max_depth = 2,
+		.frmsize = {
+			.min_width = FMT_MIN_WIDTH,
+			.max_width = FMT_UHD_WIDTH,
+			.step_width = MB_DIM,
+			.min_height = FMT_MIN_HEIGHT,
+			.max_height = FMT_UHD_HEIGHT,
+			.step_height = MB_DIM,
+		},
+	},
+};
+
 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
 {
 	struct hantro_dev *vpu = dev_id;
@@ -548,8 +589,8 @@  const struct hantro_variant rk3288_vpu_variant = {
 
 const struct hantro_variant rk3328_vpu_variant = {
 	.dec_offset = 0x400,
-	.dec_fmts = rk3399_vpu_dec_fmts,
-	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
+	.dec_fmts = rockchip_vdpu2_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
 		 HANTRO_H264_DECODER,
 	.codec_ops = rk3399_vpu_codec_ops,
@@ -560,6 +601,11 @@  const struct hantro_variant rk3328_vpu_variant = {
 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
 };
 
+/*
+ * H.264 decoding explicitly disabled in RK3399.
+ * This ensures userspace applications use the Rockchip VDEC core,
+ * which has better performance.
+ */
 const struct hantro_variant rk3399_vpu_variant = {
 	.enc_offset = 0x0,
 	.enc_fmts = rockchip_vpu_enc_fmts,
@@ -579,8 +625,8 @@  const struct hantro_variant rk3399_vpu_variant = {
 
 const struct hantro_variant rk3568_vpu_variant = {
 	.dec_offset = 0x400,
-	.dec_fmts = rk3399_vpu_dec_fmts,
-	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
+	.dec_fmts = rockchip_vdpu2_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 	.codec = HANTRO_MPEG2_DECODER |
 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 	.codec_ops = rk3399_vpu_codec_ops,
@@ -596,8 +642,8 @@  const struct hantro_variant px30_vpu_variant = {
 	.enc_fmts = rockchip_vpu_enc_fmts,
 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 	.dec_offset = 0x400,
-	.dec_fmts = rk3399_vpu_dec_fmts,
-	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
+	.dec_fmts = rockchip_vdpu2_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 	.codec_ops = rk3399_vpu_codec_ops,