Message ID | 20210330173348.30135-16-p.yadav@ti.com (mailing list archive) |
---|---|
State | Superseded, archived |
Headers |
Received: from vger.kernel.org ([23.128.96.18]) by www.linuxtv.org with esmtp (Exim 4.92) (envelope-from <linux-media-owner@vger.kernel.org>) id 1lRIIK-004pRt-QT; Tue, 30 Mar 2021 17:36:49 +0000 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232674AbhC3RgS (ORCPT <rfc822;mkrufky@linuxtv.org> + 1 other); Tue, 30 Mar 2021 13:36:18 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53484 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232677AbhC3Rfr (ORCPT <rfc822;linux-media@vger.kernel.org>); Tue, 30 Mar 2021 13:35:47 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHZU9p081116; Tue, 30 Mar 2021 12:35:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125730; bh=ewQUu325okFcaLjgG8+e0h6OWIBSBc+EpQyni7KIvkA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mpb/IeNPzO+DKsd/Z2BvZiVCfg67vsDlwsvKqNk5h7h0yA5MoPSXJ3pGI+daz/fOK I3QXzMZwIz3aXv7hMKC8hFhXYRVWQmkdR1Xw/kxS71m9x9t4dHA/CyVo4pC7o1OJ8b QlJhrAKuxYWmGqS0yGpZtXjB/QuXmRg2xmQjL8vw= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHZUwE034861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:35:30 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:30 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:30 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgw125244; Tue, 30 Mar 2021 12:35:24 -0500 From: Pratyush Yadav <p.yadav@ti.com> To: Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Peter Ujfalusi <peter.ujfalusi@gmail.com>, Maxime Ripard <mripard@kernel.org>, Benoit Parrot <bparrot@ti.com>, Hans Verkuil <hverkuil-cisco@xs4all.nl>, Alexandre Courbot <acourbot@chromium.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Stanimir Varbanov <stanimir.varbanov@linaro.org>, Helen Koike <helen.koike@collabora.com>, Michael Tretter <m.tretter@pengutronix.de>, Peter Chen <peter.chen@nxp.com>, Chunfeng Yun <chunfeng.yun@mediatek.com>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <dmaengine@vger.kernel.org> CC: Pratyush Yadav <p.yadav@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Subject: [PATCH 15/16] dt-bindings: phy: cdns,dphy: make clocks optional Date: Tue, 30 Mar 2021 23:03:47 +0530 Message-ID: <20210330173348.30135-16-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: <linux-media.vger.kernel.org> X-Mailing-List: linux-media@vger.kernel.org X-LSpam-Score: -2.5 (--) X-LSpam-Report: No, score=-2.5 required=5.0 tests=BAYES_00=-1.9,DKIMWL_WL_HIGH=0.001,DKIM_SIGNED=0.1,DKIM_VALID=-0.1,DKIM_VALID_AU=-0.1,HEADER_FROM_DIFFERENT_DOMAINS=0.5,MAILING_LIST_MULTI=-1 autolearn=ham autolearn_force=no |
Series |
CSI2RX support on J721E
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Commit Message
Pratyush Yadav
March 30, 2021, 5:33 p.m. UTC
The clocks are not used by the DPHY when used in Rx mode so make them
optional.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 --
1 file changed, 2 deletions(-)
Comments
Hi Pratyush, Thank you for the patch. On Tue, Mar 30, 2021 at 11:03:47PM +0530, Pratyush Yadav wrote: > The clocks are not used by the DPHY when used in Rx mode so make them > optional. Isn't there a main functional clock (DPHY_RX_MAIN_CLK in the J721E TRM) that is needed in RX mode ? > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > index d1bbf96a8250..0807ba68284d 100644 > --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > @@ -33,8 +33,6 @@ properties: > required: > - compatible > - reg > - - clocks > - - clock-names > - "#phy-cells" > > additionalProperties: false
On 02/04/21 01:31PM, Laurent Pinchart wrote: > Hi Pratyush, > > Thank you for the patch. > > On Tue, Mar 30, 2021 at 11:03:47PM +0530, Pratyush Yadav wrote: > > The clocks are not used by the DPHY when used in Rx mode so make them > > optional. > > Isn't there a main functional clock (DPHY_RX_MAIN_CLK in the J721E TRM) > that is needed in RX mode ? That clock is different from the clocks being used in this binding. The "psm" clock is for the PMA state machine (the internal state machine for the DPHY). The divider for this clock should be set such that the resultant clock is as close to 1 MHz as possible. This can be done either by programming the register value or by setting the correct value on the psm_clock_freq pin. On J721E the pin already has the correct value so there is no need for setting it via the register. The other clock is "pll_ref" which is used to set the input clock divider. Setting this divider is part of the DPHY TX programming sequence but is not part of the RX programming sequence. I'm not sure what exactly the divider does but I think it is supposed to divide the clock from the input stream to the TX DPHY to make sure the internal state machine is running at the correct speed. Anyway, it is not needed on the RX side because for that there is another register used (see cdns_dphy_rx_get_band_ctrl() in patch 4). The DPHY_RX_MAIN_CLK does eventually get divided into the PSM clock but it is not used directly. > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- > > 1 file changed, 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > > index d1bbf96a8250..0807ba68284d 100644 > > --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > > +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml > > @@ -33,8 +33,6 @@ properties: > > required: > > - compatible > > - reg > > - - clocks > > - - clock-names > > - "#phy-cells" > > > > additionalProperties: false > > -- > Regards, > > Laurent Pinchart
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index d1bbf96a8250..0807ba68284d 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -33,8 +33,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - "#phy-cells" additionalProperties: false